Xilinx EDK delivers processing peripheral IP Cores at no additional cost

Xilinx has expanded its catalog of no-fee intellectual property (IP) cores for designing embedded processing systems with Xilinx platform FPGAs. The 10/100 Ethernet MAC Lite, single precision floating-point unit, industry standard UART (Universal Asynchronous Receiver/Transmitter) 16450/16550 controller and IIC (Inter-Integrated Circuit) interface IP cores can now be licensed at no charge.

Made available through the Xilinx Embedded Development Kit (EDK), the four IP cores have been ported to the enhanced on-chip CoreConnect bus structure, the Processor Local Bus version 4.6 (PLB46) that Xilinx introduced last November, to be implemented in designs using the award winning MicroBlaze soft processor and the PowerPC processor embedded in the Virtex family of FPGAs.
In addition to the no-fee IP cores, numerous other value-core options are available separately from Xilinx and partners including a Tri-Mode Ethernet MAC, USB2, CAN (Controller Area Network), and the FlexRay controller.

The IIC interface IP core provides an industry standard two wire, peer-to-peer serial bus interface for device communication. This core provides master, slave and multi-master operations, supporting 400 KHz fast mode and 100KHz standard mode. The UART 16450/16550 IP core works in both 16450 and 16550 modes and performs the parallel to serial conversion on characters received from a CPU and serial to parallel conversion on characters received from a microprocessor peripheral.

Optimized to provide the basic Ethernet functions with the least resources used, the 10/100 Ethernet MAC Lite supports IEEE 802.3 Media Independent Interface (MII) to industry standard Physical Layer (PHY) devices and communicates to a processor via a Processor Local Bus (PLB46) interface. This core provides interfaces for both 10 Mbps and 100 Mbps.

The MicroBlaze soft processor has an optional configuration for implementing floating-point support via the automated Platform Studio tool suite. By comparison, the Xilinx auxiliary processor unit (APU) floating-point unit IP core is designed specifically for the PowerPC 405 hard processor core implemented in the Virtex-4 FX family of FPGAs. This core provides support for IEEE 754 floating-point arithmetic operations in single precision. Software applications can use native PowerPC processor floating-point instructions to achieve sustained performance of up to 100 MFLOPS (million floating-point operations per second.)

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