Design tools suite provides improvements in productivity, performance & power

Xilinx has introduced the delivery of its ISE Design Suite10.1, a single unified release providing FPGA logic, embedded and DSP designers with immediate access to the company’s entire line of design tools with full interoperability. The ISE Design Suite 10.1 delivers significantly faster implementations with an average of 2X faster run times, allowing designers to complete more turns per day. Significant to today’s release is the introduction of SmartXplorer technology, developed specifically to address the top challenges of the design community – timing closure and productivity. SmartXplorer technology leverages distributed processing across multiple Linux machines to enable even more implementation runs per day, and up to 38 percent faster performance by leveraging distributed processing and multiple implementation strategies. SmartXplorer technology also provides tools that allow users to monitor each run with individual timing reports.

With the availability of the PlanAhead Lite tool in ISE Foundation, users have access to a subset of the powerful floorplanning and analysis capabilities of the award winning PlanAhead design and analysis tool. Included at no additional cost, PlanAhead Lite features the revolutionary PinAhead technology, an intuitive solution designed to simplify the complexities of managing the interface between the target FPGA and PCB. PinAhead technology facilitates early and intelligent pinout definition to eliminate many of the pinout related changes that typically happen downstream by performing design rule checks during interactive pin placement. Once the pin assignments have been completed, PinAhead provides the ability to export I/O port information through either comma separated value (CSV) files or via VHDL or Verilog headers.

With ISE Design Suite10.1, Xilinx has also simplified the process of determining optimal implementation settings. Designers now have the ability to specify and set their own unique design goals, whether they are working to maximize performance, optimize device utilization, reduce dynamic power, or minimize implementation time. Designers using this area reduction strategy can realize an average of 10 percent better logic utilization.

Xilinx