NXP Semiconductors and IPextreme launch methodology for semiconductor IP design
(Technology News, 09 Apr 2008 )
Ipextreme and NXP Semiconductors announced the availability of NXP’s internally-developed CoReUse methodology and QCore tool for licensing to the entire semiconductor industry through IPextreme.
CoReUse represents more than ten years of investment by NXP to develop a comprehensive, practical, and efficient system that can be deployed at the group and enterprise level for engineers to develop reusable, high quality IP. It is in use today by nearly every NXP design group worldwide as the standard by which IP is developed and shared across the company.
CoReUse consists of a series of specifications, guidelines, and templates that guide engineers in developing reusable digital, analog mixed signal (AMS), and RF IP and includes the following:
· CoReUse Foundation. A set of reference manuals that include the CoReUse Standard and Constraints which define directory structures, naming conventions, and quick reference cards for Verilog and VHDL designs. · Design for test (DfT) specifications for CTAG/IEEE 1500, and support for testing AMS and high-speed IO technologies. · An additional set of specifications targeted for AMS and RF IP. · System level specifications for transaction level modeling, SoC integration using SPIRIT IP-XACT, and PSL assertions. · Architectural level specifications for using on-chip busses allowing the creation of IP-based platforms. · Documentation templates for engineers to capture key information about the IP they are developing.
An important companion to the CoReUse standard is QCore, an EDA tool internally developed by NXP to automatically check an IP’s deliverables and documentation for compliance to the standard. QCore produces a certificate that classifies IP according to its compliance level to the CoReUse standard allowing integrators to know the level of completeness and quality achieved by that IP.
