Renesas Technology to release new low-power SRAM products
(Product News, 16 Apr 2008 )
Renesas Technology has announced the development of the R1WV6416R Series of 64 Mbit Advanced Low-Power SRAM (Advanced LPSRAM) products with the highest LPSRAM capacity currently available, and the R1LV3216R Series of 32 Mbit Advanced LPSRAM products with compact chip size. Sample shipments of the 32 Mbit products will begin in April 2008, and of the 64 Mbit products in July, in Japan.
These two new series will further extend Renesas Technology’s lineup of Advanced LPSRAM products employing exclusive memory cell technology to achieve smaller chip sizes and soft error free.*1 They will be available in different packages and specifications, such as access time, for a total of twelve 64 Mbit products and eight 32 Mbit products to meet a wide range of requirements in fields including industry, office equipment, consumer electronics, automotive systems, and communications equipment.
The main features of the R1WV6416R Series and R1LV3216R Series are summarized below.
· Low-power SRAM with industry’s largest capacity of 64 Mbits The new 64 Mbit low-power SRAM products each comprise a stack of two compact 32 Mbit Advanced LPSRAM chips in a single package, resulting in the highest capacity in the industry. They meet demand for larger-capacity low-power SRAM for high-performance systems and meet reduced space requirements in applications that previously would have required multiple low-power SRAM devices.
· Extensive package lineup to meet a wide range of requirements To accommodate a variety of applications, these two new series are being offered in several different packages: TSOP I (48-pin), μTSOP (52-pin), and for 64 Mbit products FBGA (48-ball). The TSOP I and μTSOP packages have the same dimensions as those of previous 16 Mbit products, and the ball layout of the FBGA package is signal pin compatible. This enables customers to increase memory capacity while continuing to use their existing layout designs.
· High reliability with soft error free and latchup free Advanced LPSRAM uses a stacked capacitor*2 memory cell configuration, an approach with a proven track record in DRAM cells. It virtually eliminates soft errors caused by alpha radiation or high-energy neutron radiation, which can be a problem with ultrafine SRAM. In addition, this memory cell configuration avoids the unintended formation of an parasitic thyristor,*3 which can generate spurious current flows and cause latchups. Elimination of soft errors and latchups provides excellent reliability.
