16-bit, 105Msps serial output ADC conserves FPGA I/O pins
(Product News, 18 Apr 2008 )
Linear Technology Corporation announces a 16-bit, 105Msps ADC that establishes a simple, new benchmark for digital communication between high speed ADCs and FPGAs. The LTC2274's new high speed 2-wire serial interface greatly reduces the number of data input/output (I/O) lines required between a 16-bit ADC and the FPGA from 16 CMOS or 32 LVDS parallel data lines to a single, self-clocking, differential pair communicating at 2.1Gbps, freeing up valuable FPGA pins.
Serial data communications offers simplified layout, and requires less board area for routing, while providing the flexibility to route across analog and digital boundaries. In noise sensitive applications, the serial interface provides an effective isolation barrier between digital and analog circuitry and serves to eliminate coupling between digital outputs to reduce digital feedback.
The LTC2274 output data is serialized according to the JEDEC serial interface specification for data converters (JESD204) using 8b10b encoding, and is compatible with many FPGA high speed interfaces including Xilinx's Rocket IO, Altera's Stratix II GX I/O and Lattice's ECP2M I/O. At 2.1Gbps, the LTC2274 offers the fastest high speed serial interface of any ADC on the market today. Applications such as leading edge communications equipment, multi-channel systems, space-constrained designs, and instrumentation all benefit from the LTC2274's unique interface and feature set.
