Talus QDRC integrates DRC into implementation for 65- and 45/40nm designs
( 01 May 2008 )
Magma Design Automation’s Talus QDRC is a physical design verification product that improves productivity and time to market for 65- and 45/40nm designs by identifying and correcting design rule violations during implementation. Unlike prevailing DRC methods that require streaming data from an implementation database – resulting in missed errors that require design rework, lengthening the design cycle of today’s complex devices significantly – Talus QDRC decreases overall design costs by addressing Design Rule Check (DRC) problems before they delay design tapeout. Talus QDRC is currently deploying on 65- and 45/40-nm designs.
Talus QDRC operates systematically during implementation, reducing the post-implementation DRC sign-off effort and shortening the final physical design verification stage of chip development. Talus QDRC has access to all layout layers with IP reference views to identify common problems that can affect final sign-off downstream in the flow, including LEF-versus-GDS mismatch; problems with metal fill; and open/short detection. It also saves cycle time by eliminating the need to stream data out of and back into the implementation flow for DRC or layout versus schematic (LVS) analysis.
Talus QDRC helps minimize the time and costs of implementing DRC-clean designs. It allows designers to run checks using foundry-certified design-rule runsets directly on blocks without having to stream out the data in GDSII format. Reference-level IP views of all GDS layers can be generated making debugging easy. A powerful debugging user interface exposes DRC issues systematically. ECO changes are handled with a new incremental capability that uncovers DRC checks in minutes rather than hours or days, working on just the changed portion of the design. Talus QDRC’s unique pipelined architecture scales linearly with the addition of more CPUs, shortening execution times without requiring costly machines.
