By Mrinal J. Sarmah, Guru Prasanna & Usha Priyadharshini, Xilinx India Technology Services
The current industry trend is to switch from parallel connectivity to serial. This is being driven by companies across a wide range of industries as a means to reduce system costs, simplify system design, and provide scalability to meet new bandwidth requirements, smaller form factor, fewer PCB traces and lower pin/wire count. Serial solutions will be deployed in nearly most aspects of every electronic product imaginable, from chip-to-chip interfacing, backplane connectivity and system boards to box-to-box communications in foreseeable future.
An integral part of Xilinx’s flagship Virtex-5 platform FPGA are the 5.0Gbps transceivers. Used in multiples, these transceivers support a throughput of 120Gbps and above. Serial communication protocols employ line encoding schemes to ensure sufficient transition and alignment of the input data stream. The widely adapted 8B/10B encoding scheme used by some of the popular serial communication protocols such as fiber channel and 1G Ethernet, constitutes an overhead of 25% of the bandwidth. In order to increase the bandwidth efficiency, other forms of line encoding schemes have emerged. The notable among them is the 64B/66B encoding scheme.
Aurora 64B/66B Protocol is a result of Xilinx’s "High-Speed Serial Initiative" to significantly expand its suite of serial connectivity solutions to enable system designers to build next-generation products that take full advantage of high-bandwidth connectivity while adhering to current parallel I/O standards. This scalable, lightweight, link-layer protocol for point-to-point serial data transfer is a free, protocol agnostic, customizable, open protocol that can be implemented in any silicon device/technology. It provides a transparent interface to the physical serial links, allowing upper layers of proprietary or industry-standard protocols, such as Ethernet and TCP/IP, to easily use these high-speed serial links.
Challenges
Looking at the advantages Aurora 64B/66B can bring, this IP core is architected, designed, supported and wholly owned by Xilinx Systems Engineering Group (SEG) based in Hyderabad, India. Two aspects that the design team in Hyderabad was looking for were optimization across speed and area. The target resource count for this IP was aimed at half that of existing similar IPs with an added benefit of throughput improvement and efficient line coding. The design team analyzed similar solutions provided by Xilinx and other vendors in an effort to provide the customer with a low cost robust solution that cater to their applications.
Another design challenge emerged when channel bonding and clock correction logic for 64B/66B encoding was to be implemented in fabric because of transceiver limitations. The team explored various channel bonding procedures and came up with one that fitted into the current implementation of the aforesaid IP that would save lot of bonded IOBs and logic count.
Aurora 64B/66B is a thoroughly verified IP core which Xilinx released as a part of Coregen IP. To abridge time-to-market, the verification team started developing the Behavioral Functional Model (BFM) for the protocol almost when design cycle started. The aim of developing a separate soft functional model was to test data integrity and protocol conformance of the design-under-test (DUT) in the Aurora 64B/66B core. BFM is OOPs based, uses strengths of IDF parsing, and has the capability of employing huge stack of test metrics consisting of random test vectors. BFM can inject error to DUT thereby ensuring a thorough verification of DUT’s state transition during initialization phase. The model can introduce programmable skew in multiples of bit period across various lanes, and the external channel bonding logic in DUT is tested using this capability set of BFM. DUT is regressed through a number of directed and random test cases. In a typical scenario of DUT-BFM testing, functional coverage is ensured by random contribution each from DUT and BFM. 1622 (possible design combinations) x287 (test vectors for each design) random vectors test DUT’s robustness when it undergoes BFM regression.
The IP core is supplemented with traffic generator and checker modules that can inject all kinds of interface traffic. A board-level team validated the entire design metrics of Aurora 64B/66B IP using pseudo-random pattern generators. A custom-made Xilinx development board with a Virtex-5 FPGA device on board was used for hardware testing. The validation team created a full suite of test cases aiming for 100% conformance passes at first level.
To shorten the development and debug life cycle of the IP, the Xilinx team used short-hand techniques for automating the verification flow, configuration of environment variables for various project settings, etc. The automation flow is a unified flow and the result database is comprehensive enough and debug friendly. This centralized database enabled local and overseas project management tracking of the project. For bug tracking, the team used Xilinx issue request tools and its dashboard measures.
Conclusion
Xilinx’s SEG group in Hyderabad delivered a protocol compliant, configurable Aurora 64B/66B IP core within a tight project schedule from architecture to productization, the complete life cycle. A single lane Aurora 64B/66B design consumes about 566 flip-flops and 377 LUTs in a Virtex-5 FXT device, which is almost near to estimated count. Full lifecycle development of a complete IP like Aurora 64B/66B is an example of the exciting work environment at Xilinx’s India Development Center.
