XMOS programmable chips bring flexibility and differentiation at low cost
(Product News, 25 Apr 2008 )
XMOS Semiconductor has announced its first family of programmable chips. The XS1-G product family comprises three devices offering a choice of 1,2 or 4 of the company’s XCore event-driven, multi-threaded processor tiles and are priced at $1-10 in volume.
Employing an entirely software based design flow that uses C and the XMOS originated XC programming language, XS1-G eliminates the delays involved in classic hardware description languages and low level logic synthesis. The first device to be made available by XMOS will be the quad-XCore, XS1-G4.
XS1-G devices suit products requiring programmable flexibility and differentiation but which cannot support the relatively high cost of traditional programmable logic solutions. Typical SDS applications include set-top boxes, home networking, display panel control, toys, and consumer electronics. The XMOS chips can significantly augment the function of standard product ICs, ASICs, SOCs and FPGAs, or be used to implement a complete system.
Each XCore 32-bit RISC processor engine offers designers up to eight threads and is integrated with all the required support resources into a building block called the XCore tile. Event-driven and tightly coupled to a highly flexible intelligent I/O pin structure, the XCore processor delivers up to 400MIPs per tile, enabling implementation of concurrent real-time hardware and software functions, ranging from simple I/O interfaces through to complete software applications.
A total of 64 user definable I/Os are provided per tile, offering a mix of 1, 2, 4, 8 16, and 32 bit bi-directional SERDES integrated ports. Memory resources include 64KBytes of SRAM for user code and 8KBytes of OTP memory. 32 XLink 1Gbps channel ends interconnect adjacent XCore tiles and enable threads to interact without the disadvantage of shared memory systems. An embedded hardware thread scheduler dynamically selects threads for execution, providing kernel-level control capabilities.
Designs for XS1-G devices use an embedded software development flow. Two compilers target the XCore processor engine – an ANSI C Compiler from ACE Associated Compiler Experts and the XMOS XC compiler. A mapper/linker builds object files from the source code and precompiled IP modules. The two compilers are seamlessly integrated for mixed C and XC projects. XC is an XMOS-originated variant of C that supports parallel processing, event-driven control and time-based programming. A companion Eclipse IDE provides developers with a complete debug and simulation environment.
To further reduce product development times, XMOS Semiconductor provides a range of pre-compiled, pre-verified Software Components providing fast access to a wealth of proven intellectual property. Interface IP currently available ranges from an SRAM interface through to a 10/100 Ethernet MAC, while the software stack selection includes 128-bit AES encryption and FIR filtering.
