TI introduces high-performance 16-bit, 800 MSPS dual-channel digital-to-analog converter for 3G and 4G communications
(Product News, 02 May 2008 )
Texas Instruments Incorporated has introduced a 16-bit, dual channel, 800 MSPS digital-to-analog converter (DAC). The new device builds on the field-proven design of the DAC5687 and continues to push the space and performance boundaries in transmit DAC solutions for wireless base stations, software-defined radio applications and multi-frequency test equipment (See http://focus.ti.com/docs/prod/folders/print/dac5688.html.)
The DAC5688 expands on TI’s portfolio of full-featured DACs and represents a 67 percent space reduction over the previous generation. Offered in a space-saving 64-pin 9 mm x 9 mm QFN package, the DAC5688 features enhanced performance to support existing 3G applications, including WCDMA and TD-SCDMA, and emerging 4G applications, including WiMAX and LTE. For instance, for an output frequency of 70 MHz, the device achieves 81 dBC ACLR for a single-carrier WCDMA application.
To further enhance performance in communications design, the DAC5688 allows for more exact frequency placement, superior linearity, noise crosstalk and PLL phase noise performance. An optional frequency mixer with a 32-bit numerically controlled oscillator (NCO) runs up to 800 MHz, enabling more exact frequency placement. A digital inverse SINC filter compensates for natural DAC sin (x)/x frequency roll-off. In addition, the digital quadrature modulator correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection to create a flatter pass band. An integrated 2x-32x clock multiplying PLL/VCO offers lower jitter and four times the multiplying range over the DAC5687. This extended range can enable designers to operate with simpler external clocking, reducing complexity and cost.
To increase flexibility, the DAC5688 dual CMOS data bus provides 250 Mbps input data transfer per DAC channel. Several input data options are available including dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock, which eases interface timing. Input data can be interpolated two, four or eight times by on-board digital interpolating FIR filters with greater than 80dB stop-band attenuation.
