In most applications, the 
(manual-reset) pin usually connects to a switch to create a manual-reset signal to the supervisory chip. Subsequently, after a predetermined time-out-active period, it goes back to the high state in an active-low reset. A manual reset is a good feature for most applications; however, it requires human intervention to create the reset. In some applications, a manual reset could be a hassle because you must perform it each time the system powers up.
Further, applications involving embedded microprocessors can require the reset output to hold high—that is, inactive—for a certain period of time before you can apply the reset, or active low. The circuit in Figure 1 proves useful during power-up when there is no need to press the reset button once the device powers up, because reset occurs automatically with the predetermined hold time before you apply the reset-low signal.
The circuit employs a reset-supervisory chip with the pin and active-low output, . Normally, the 
input has an internal pullup resistor with a value of 20 to 50 kΩ. During power-up, this internal resistor charges up capacitor C1 to the maximum value to VDD at the positive side. To create an reset input to the supervisory chip, its input must receive an active-low ground signal, requiring transistor Q1 to turn on. The turn-on-time period depends on the RC-time constant of R1 and C2. These two components determine when Q1 turns on and thus provide an adjustable hold time for the output to hold high. To increase the hold time, simply increase the RC-time constant of R1 and C2.
The supervisory reset chip asserts its output only when the voltage at the pin exceeds the threshold-trigger voltage and the supervisor’s internal reset period has elapsed. This time-out period filters any short input-voltage transients. Because of Q1’s turn-on, the negative side of C1 becomes grounded. Because the positive side of C1 cannot instantly change its polarity, it pulls low and slowly charges up again through the internal pullup resistor of the input. When it reaches the threshold voltage of the reset chip, it then asserts the reset once it reaches the time-out period of the chip. The selection of C1 is not critical. However, its value should be sufficiently large—0.1 to 10 µF, for example—that the RC time constant for C1 and the internal pullup resistor are large enough. This value ensures that C1 holds the voltage low at for at least 1 µsec.
The transistor remains on after C2 charges toward the biased voltage of Q1. At the next power-up or when you manually reset the circuit by pressing the pushbutton switch, the transistor discharges C2. Once this action happens, Q1 turns off. R1 charges up the negative side of C1 to the supply voltage, VDD. Because the positive side of capacitor C1 cannot change instantly, it appears to be charged to 2VDD. However, the protection diode, D1, clamps C1’s voltage to just VDD plus the diode’s turn-on voltage. The cycle repeats once C2 charges enough to again turn on Q1.
Click here for Illustrations:
Figure 1
Click here for Illustrations:
Figure 1
