Modern FPGAs are playing an important role in small processor based systems, which are mostly used in communications, data processing, and networking applications.
One of most important tasks in such systems is the interface with analog signals.
By adding some basic analog I/O and on-chip transducers to FPGAs, they can be configured to monitor on and off chip environment parameters and pass this information to the host computer along with other information concerning external power supply and thermal conditions. These analog conditions include external operating environments such as temperature, humidity, and power fluctuations; or on chip conditions such as on-chip temperature, internal voltage levels, etc.
The continuous monitoring of various transducer inputs can be managed by using either a soft microprocessor core or a simple state machine. When the monitored parameters violate the normal operating range, only the host computer will be interrupted. This avoids any adverse conditions by taking corrective action such as triggering the FPGAs and/or the complete system going in to power down mode interrupting the host processor.
The Xilinx Virtex-5 series of FPGAs provide system-monitoring capability by having SYSMON hard macro located at the center of the FPGA. The Virtex-5 SYSMON hard macro function (Figure 1) is built around a 10-bit, 200kSPS (kilo-samples/second) analog-to-digital converter (ADC) with a resolution of 1mV.
When combined with a number of on-chip sensors, the ADC is used to measure the FPGAs physical operating parameters such as on-chip power supply voltages and die temperatures. The ADC produces a full-scale 10-bit code (3FFh) with 1V differential input voltage on its external analog inputs. Access to external voltages is provided through a dedicated analog differential-input pair (VP/VN) and 16 user-selectable analog inputs, known as auxiliary analog inputs (VAUXP [15:0], VAUXN [15:0]). The external analog inputs allow the ADC to monitor the physical environment of the board, or enclosure. The dedicated analog inputs and the auxiliary analog inputs can be driven either single ended or as truly differential sources.
Configuration options
The SYSMON hard macro is instantiated in the user system and configured via a number of configuration registers. These registers typically control the different operating modes of SYSMON hard macro, such as:
• adjusting calibration coefficients to the ADC,
• configuring in single channel event triggering or continuous cycling mode as well as continuous cycling mode,
• varying the sampling frequency of internal ADC,
• averaging the on-chip parameter measurements, and
• configuring FPGA to going into power down mode
A register-file-based (128 16-bit registers) interface through JTAG TAP or fabric allows easy access to the measured data and the SYSMON hard macro Control Registers.
To monitor a single channel, the SYSMON can be configured in the Single Channel Event Driven Mode or Single Channel Continuous Cycling Mode.
The Single Channel Event Driven Mode can be controlled internally by providing an active high pulse to internal conversion start signal, or externally by providing a single clock wide active high pulse on CONVST input pin.
The Continuous Cycling Mode monitors all or some of the 17 analog channels.
The sequence of the channels to be monitored can be set by configuring the Sequence Register of the SYSMON hard macro. The measured values for both on-chip sensors and external channels are read after completion of the ADC conversion. The Status Registers store the maximum and minimum measurements for each of the on-chip sensors.
The SYSMON hard macro ensures accuracy over environmental conditions and time, if auto calibration is enabled. Automatic calibration and self check features ensure accurate and reliable measurements over a temperature range of -40° to +125°C.
Using alarms in SYSMON
The SYSMON hard macro provides user programmable alarm thresholds (upper and lower limits) for the various on-chip sensors such as on chip temperature, VCCaux, Vccint etc. These threshold values can be provided by configuring the Threshold Registers in the SYSMON hard macro. Thus, if any of the on-chip monitored parameters move outside of the user-specified operating range, the related alarm output becomes active. The alarm signals of the SYSMON hard macro can be connected to the system interrupt pins to raise the alarm of any critical situation. These alarms are automatically deactivated when the measured parameters fall in the assigned range.
The power down mode is optional and can be activated if the FPGA on-chip temperature goes above 125°C by initializing a special alarm called Over Temperature (OT). The over-temperature signal is deactivated when the device temperature falls below a user-specified lower limit.
JTAG access to the SYSMON registers
All SYSMON hard macro features are customizable at run time through the Dynamic Reconfiguration Port (DRP) and the SYSMON hard macro Configuration Registers (Control Registers).
The access to the DRP is either through the external JTAG TAP port, or through the soft IP such as XPS Sysmon ADC, which is available in latest EDK toolkit (EDK 9.2i onwards).
The JTAG interface can be provided either through the ISE tool (ISE 9.2i onwards) (as shown in Figure 2), or with a simple TCL script, which runs on the XMD command prompt. The JTAG interface provides full Read/Write access to the SYSMON hard macro register file interface. After power-up, the SYSMON hard macro operates in the safe mode and its functionality can be customized, if required, through the JTAG TAP. These control registers can also be initializable at design time when SYSMON hard macro is instantiated in a design.
The external access to the register file based interface through JTAG TAP can be monitored by referring the status of JTAG specific signals from SYSMON hard macro. The SYSMON arbiter allows either JTAG access or the DRP access using soft IP at a given time.
Configuring Virtex -5 SYSMON using Xilinx ISE Tools
The Xilinx ISE (ISE 9.2i onwards) tool provides a direct method to configure the SYSMON in the desired mode for any particular application with out going through the above mentioned method. T
The SYSMON hard macro can be initialized in the user design by using the “IP Coregen & Architecture Wizard” option from the “New Source Wizard” sub-menu of “Project” menu option in the ISE tool.
The System Monitor Wizard v1.0 can be found in the “FPGA Features and Design” option. The “System Monitor Wizard” (as shown in Figure 3) is the most effective tool to configure the required set of registers, channels, different operating modes and the sequence of the channels, threshold values of registers, setting up the alarms, ADC calibration, inclusion/exclusion of DRP, CONVST, external analog inputs etc.
At the end of configuration the wizard will generate the HDL source, which is effectively a part of the system, which uses the SYSMON functionality.
Using the Chip Scope Tool SYSMON Parameter Monitoring
Xilinx Chip Scope tool (ISE 9.2i onwards) is capable of providing a GUI interface with the SYSMON hard macro. It communicates with the SYSMON macro through the JTAG interface when the FPGA is powered up. This option of SYSMON configuration and monitoring is used even before the FPGA is configured. It automatically detects the presence of SYSMON on the JTAG chain and allows user to display the measurement data. The user can modify the Configurable Registers, Sequence Registers and the Threshold Registers through GUI any time during the course. The tool allows setting the depth and the window of the measured parameters. The user can save the measured data along with the time stamp in a log file for separate analysis. Refer Figure 4 for more information.
To achieve the best possible performance and accuracy with all measurements (both on-chip and external), six dedicated pins are provided for the ADC reference and power supply (refer Figure 5 for dedicated pins). Care must be taken with the connection of these pins to ensure the best possible performance from the ADC. For typical usage, the reference voltage between VREFP and VREFN should be maintained at 2.5V ± 0.2% using an external reference IC.
Disabling the Virtex-5 System Monitor
The choice of inclusion of the SYSMON hard macro in the Virtex-5 based systems is optional. The SYSMON hard macro operates even though it has not been instantiated in a design as well as prior to the FPGA configuration. This default operating mode allows the SYSMON hard macro to measure on-chip temperature and voltages only.
It is also possible to use the SYSMON hard macro as a dedicated general-purpose ADC in an application by disabling the monitoring of the on-chip sensors. If not used in the system, the SYSMON hard macro should be disabled to save the power consumption. The SYSMON hard macro can be permanently disabled, by connecting its dedicated supplies and input pins to ground (as shown in Figure 5).
Conclusion
The analog interface capability has added benefits of using FPGA based systems. Think how to use the
SYSMON can be used in simple state machine based designs and can be further extended as an independent solution for different applications.
References
Virtex-5 System Monitor User Guide, UG192
XPS Sysmon ADC IP Core (v1.00.a) (DS620)
About the Author
Sanjay Kulkarni is a member of the processor IP development team in Xilinx India Technology Services Pvt. Ltd., Hyderabad, India. He can be reached at sanjayk@xilinx.com
Captions
Figure 1: System monitor (SYSMON Hard Macro) block diagram.
Figure 2 : System monitoring using Virtex-5 FPGA.
Figure 3: Configuration of SYSMON using system monitor wizard in Xilinx ISE tools.
Figure 4: SYSMON access via the JTAG interface and chip scope tool.
Figure 5: Disabling the Virtex-5 FPGA system monitor function.
Click here for the illustrations:
Figure 1, Figure 2, Figure 3, Figure 4, Figure 5
