Today industry segment faces many challenges from different sides: there are constantly increasing efficiency requirements mainly driven by environmental energy efficiency concerns, and increasing power density requirements driven by trends such as small and ultra small form factors for desk top PCs or increasing output power at given form factors, for eg front end power supplies for server applications. In consumer applications we see trends towards the fusion of computing and entertainment equipment leading to more stringent EMI compliance and ESD ruggedness requirements. And last but not least solutions have to be cost effective, which pushes towards lower material costs and standardization.
Challenges and solutions
Efficiency
In the few years back, the efficiency of power supplies has mainly been a thermal design aspect to avoid overheating of components in the power supply. Therefore main focus has been on full load efficiency at low line condition. Today this operation point is still important but partial load efficiency covering typical operation conditions of the equipment are gaining rapidly in importance as well. This trend is visible in efficiency requirements such as 80+ demanding the efficiency beyond 80% at 20, 50 and 100% of the rated output power. In a similar way the big brands such as IBM and HP are requesting efficiency range between 80% and 90% efficiency for their server power supplies again over a wide output power range.
In the server segment, power density and efficiency are already on a very high level and the main challenge now is to improve efficiency at the partial load. One elegant solution already in the market is to separate the load regulation and isolation into two power stages. Power architectures such as Boost - buck - resonant PWM stages are gaining popularity. The main advantage here is that the PWM stage can constantly run at maximum duty cycle no matter what load condition the power supply is facing. This is the ideal condition for resonant PWM topologies such as the LLC converter and furthermore ideal for synchronous rectification as the secondary side transformer voltage is only slightly higher than the output voltage. This enables the use of much lower voltage classes for the synchronous rectification power MOSFETS eg 40V instead of the 75 to 100V used today in 12V output supplies. The drawback is on the more complex control and the efficiency loss of the additional load regulation stage. Practical implementations however show that the entire system efficiency can surpass the efficiency of conventional 2-stage approach.
Infineon Technologies is supporting this trend with its product lines CoolMOS™ CP 500V and 600V as well as with its upcoming product line-up of 40V and 60V OPTIMOS™ products which complement our already existing 100V portfolio.
In PC power supplies, the highest loss come from the secondary side rectification which still uses Schottky diodes in the majority of designs. As the power supply needs to deliver 3 different output voltages, typically 3.3V, 5V and 12V with high output currents, the solution based on synchronous rectification would require high efforts with either control ICs or self driven approaches plus MOSFETs on all three output lines. Co-driven by both efficiency requirements and the necessity to reduce the size of the power supply, the output section of the conventional silver box design will be changed towards the architecture with one distinct output voltage of 12V and subsequent DC/DC converters to produce the required 5V and 3.3V. This trend is also already visible in the market in SFX and TFX designs and will become most likely visible in high power ATX designs as well. Infineon Technologies is supporting this trend with its full range of products for both high voltage and low voltage MOSFETs.
Power density
The trend towards higher power density is derived out of the need of higher output power in given form factors such as 1U blade designs. The requirement for higher output power itself comes from improved cooling schemes of server racks facilitating the accommodation of more and more processors in one rack, which in turn lowers the space requirements in server farms for a given calculation power. As the power density in recent designs is already hitting the 30W / in³ line further improvement becomes extremely difficult, especially under the side condition of same or even better efficiency.
Easy scheme such as enhancing the PFC frequency is no longer feasible due to efficiency reduction. Interleaving PFC is also not an easy due to higher part count, but it is an option to improve efficiency at same or reduced power density.
Interleaving the PWM stage with topologies such as Interleaved-two-transistor-forward might bring advantages from the aspect of two smaller magnetic cores instead of one big one. Furthermore advantages can be gained for the synchronous rectification due to very low voltage requirements on the central free wheeling branch. As RDSon is the key requisite for synchronous rectification MOSFETs, a lower voltage class brings tremendous benefit in the achievable RDSon at a given footprint or package size. Thus power density can be improved with the reduction of the number of paralleled devices. Furthermore, it is also observed that the trend towards independently mounted daughter cards being arranged perpendicular to the main board of the power supply. In a similar way the boost-buck-PWM approach discussed above brings advantages especially on the synchronous rectification side. Space has to be accommodated however for the additional buck stage.
In a general evaluation of efficiency versus power density, we believe that at the time being the fulfillment of efficiency targets is more important than power density.
Transient noise immunity and EMI compliance
Due to the fusion of computing and entertainment functions an increasing number of consumer equipment is supplied with antennas or wire line net access, which enhances the exposure to external ESD and lightning surge stress. Improving the ruggedness of the control ICs to the transient surge events becomes therefore a crucial. Special care has therefore to be taken to prevent the IC from abnormal function. Our new enhanced version of CoolSET™ ICE3A1065LJ can stand for an extremely high ESD level up to 20 kV and lightning surge level up to 10kV based on a thorough analysis of the internal damage created by external surge events.
The need for better EMI compliance is driven both by cost / space considerations for the EMI filter as well as development time requirements as the optimization of the EMI spectrum can be a very tedious and time consuming task. In the low power range topologies such as quasi-resonant flyback become very popular. For AC input voltages of up to 260VAC, standard designs with 600V MOSFETs can not achieve real zero voltage switching and the advantage of the quasi-resonant approach is therefore not fully utilized. In order to reach real Zero-voltage-switching a blocking voltage of 900V is most favorable. The elimination of hard turn-on condition together with dv/dt relieved turn-off (from snubber network) is both favorable for efficiency and EMI spectrum.
Infineon Technologies supports this trend with its quasi-resonant IC ICE2QSXX and its brand-new CoolMOS™ 900V product portfolio.
3. Summary
Infineon Technologies helps with its unique power MOSFET portfolio and its selected ICs to overcome specific challenges in today power supply industry.
