STMicroelectronics has announced the deployment of a certified electronic system level (ESL) System-on-Chip reference design flow.
The design flow has been adopted and internally distributed following successful tape-outs of more than a dozen ASIC (application specific integrated circuit) designs with productivity gains from four to ten times faster than with traditional methods. Additionally, ST is also meeting increasing demands from industry leaders in consumer markets for complete system-level design platforms integrating digital and RF/mixed-signal technologies. A number of leading-edge ST products have been developed using this reference design flow, such as a 2-megapixel YUV CMOS image sensor and a highly-integrated image processing hardware accelerator for mobile phones.
Aimed at complex designs for next-generation consumer electronics equipment, ST’s integrated ESL reference-design flow for complex digital CMOS designs combines high-level synthesis, sequential equivalence checking, power exploration and lint checkers that look for errors in code construction, thereby providing a complete methodology from ANSI C++ to RTL including certified integration ST’s certified RTL-to-GDS2 design flow. As a result, hardware designers using ST’s ESL reference flow are able to create and verify chips faster, with higher quality.
The advanced design flow is the result of more than three years of close collaboration with best-in-class EDA providers for each of the core ESL technologies. The ST design flow is integrated with Atrenta’s industry-standard SpyGlass® for RTL lint checking and power analysis; the Mentor Graphics® Catapult® C Synthesis tool; and Calypto Design Systems’ SLEC equivalence checker, providing highly efficient synthesis from pure ANSI C++ to RTL and formally verifying that the resulting RTL implementation is functionally correct. This advanced flow provides a comprehensive solution that includes: RTL lint sign-off; power estimation and exploration; C-to-C formal equivalence checking; C-to-RTL formal equivalence checking; SystemC model generation; and C-to-RTL high-level synthesis, thereby minimizing risk and shortening design cycles with ‘real-world’ productivity gains of between four and ten times.
Additionally, ST is successfully using its design and verification flow for RF/mixed-signal ICs to accelerate the development of sophisticated mixed-signal chipsets used in multi-band, multi-format wireless products. The RF/mixed-signal design flow is based on Agilent Technologies’ Advanced Design System (ADS) software and Mentor Graphics’ Catapult C synthesis technology.
Optimized ANSI-C code, which describes the digital element of the chip, is used in Agilent’s ADS platform to verify the RF/mixed-signal design performance against published wireless standards. Once verified, this same optimized ANSI-C is then input into Mentor’s Catapult C compiler to create very high-speed integrated circuit hardware description language (VHDL) that is used for gate-level synthesis into an ASIC.
For further information on the specific CAD tools:
Agilent’s Advanced Design System - http://www.agilent.com/find/eesof-ads
Atrenta’s SpyGlass - http://www.atrenta.com/solutions/products/spyglass_power.htm
Calypto’s SLEC equivalence checker - http://www.calypto.com/slecsystemhls.php
Mentor’s Catapult C - http://www.mentor.com/products/esl/high_level_synthesis/index.cfm
STMicroelectronics
