Synopsys’ Design Compiler Graphical synthesis product shortens implementation time for system-on-chip (SoC) devices by helping RTL designers avoid wire-routing congestion problems that typically occur during detailed route. Design Compiler Graphical is said to be the industry's first synthesis solution that predicts circuit congestion "hot spots" early in the design flow, provides designers with visualization of the congested circuit regions and performs synthesis optimizations to minimize congestion in these areas. The ability to predict, visualize and alleviate routing problems prior to physical implementation substantially reduces iterations between synthesis and place-and-route, and can significantly lower project time, effort and cost.
