The SN74SSQE32882 is said to be the industry’s first full production release of a phase locked loop (PLL) integrated DDR3 register for registered dual in-line memory modules (RDIMMs). It enables system stability through constant clock and output delay over voltage and temperature variation. The 28-bit to 56-bit registered buffer operates at 1.5 V VDD and supports parity features to ensure reliability. It provides flexibility by supporting high data rates of 800 to 1,333Mbps, and can support up to 72 DRAMs on one module.
Texas Instruments, www.ti.com
