Companies are rolling out ideas to face 32nm design challenges. But it seems that dielectric is a contentious issue and designers are not sure what should be the ideal dielectric at 32nm and below designs.
IBM has announced that along with its partners, including Chartered, Freescale, Infineon, Samsung, STMicro, and Toshiba, it is “open for business” for early customer design engagements using a bulk 32nm technology with a high-k/metal gate stack. The alliance’s low-power 32nm design enablement package is now available, with a design prototyping shuttle starting in Q3 08 and continuing on a quarterly schedule. Using high-k/metal gate technology, claims this alliance, will provide cost, performance, and power savings. An IBM spokesperson explains that this technology means that “we can shrink the gates and the space between the gates, enabling better scaling than if we had used a poly/oxynitride gate stack. We can push the contact size and improve the overlay between the contact and the gate.”
UNIFIED DESIGN FOR MANUFACTURING
TSMC has announced the availability of 32nm evaluation kits and aims at rolling out its 32nm offerings in Q3 09. TSMC will offer general purpose and low-power 32nm processes with a conventional oxynitride gate oxide. The IBM alliance has criticized TSMC for using conventional oxynitride gate oxide. It explains that not using high k/metal gate technology at 32nm will make it necessary to use a costly triple oxide technology with a thin gate oxide for the high-performance logic circuits and a thick oxide to prevent leakage in the SRAM arrays. However, TSMC claims that its new Unified Design For Manufacturing (UDFM) architecture that targets 32nm process technology and smaller geometries improves yields, lowers design costs, and accelerates time-to-market and time-to-volume. UDFM, which includes a new DFM Design Kit (DDK) that for the first time encapsulates an embedded DFM software engine with an interoperable API in addition to the process-related DFM data and models, provides a unified, encapsulated access to TSMC foundry data and was developed in collaboration with EDA vendors and other design infrastructure partners. The TSMC UDFM is also one of the key collaborative components of the company's recently unveiled Open Innovation Platform, which is a platform for innovations, hosted by TSMC and open to TSMC customers and partners. It is built on TSMC's design-enabling building blocks and an ecosystem interface. TSMC's Unified DFM DDK will be available in early Q3 08 to registered members through the TSMC customer portal.
TSMC claims that the "copy exact" method compensates for increasing manufacturing variances in advanced process technologies, radically improves design alignment between simulated hotspots and actual manufacturing hotspots, and delivers timely accuracy to the design ecosystem. The new DFM architecture handles very large DFM dataset and design complexity, resulting in reduced design cycle time and faster time-to-market and volume.
The IBM alliance has reservations about TSMC claims. It seems that not all TSMC partners are convinced of TSMC dielectric stand. For instance, Sun, which announced February last that it would switch from TI to TSMC as foundry for 45nm and beyond, has now said that Sun microprocessors will use its own version of high-k dielectric and not TSMC’s.
IMEC REDUCES PROCESS STEPS
The Belgian-based research institute IMEC, whose partners include Intel, Micron, Panasonic, Qimonda, Samsung, TSMC, NXP, Elpida, Hynix, Powerchip, Infineon, TI, and STMicro, reports an improved performance for its planar CMOS using hafnium-based high-k dielectrics and tantalum-based metal gates for the 32nm CMOS node. The inverter delay advanced from 15ps to 10ps. IMEC also simplified its high-k/metal gate process by decreasing the number of process steps from 15 to 9.
I think not enough data is available for designers to come to definitive conclusion about the best approach in using dielectric and they should wait for more data to come out from foundries before drawing conclusions.
