To allow the creation of a single, integrated, low-power system-on-chip (SoC) design implementation, Santa Clara, Calif.-based EDA provider Magma Design Automation Inc. and Cambridge, England-based IP market player ARM announced a toolset that spans RTL to GDSII.
The design flow uses Magma’s Blast Power software to create the design implementation aimed at providing power reduction when the SoC is in asynchronous mode, and optimal performance when operating synchronously.
The low-power extension to the existing ARM-Magma reference methodology supports designs with multiple supply voltage domains, concurrent multi-VT optimization, power gating with MTCMOS, clock gating and multi-mode analysis and optimization.
In addition, Magma’s Blast Rail software was incorporated for static, dynamic and transient power and voltage drop analysis. Multiple voltage islands in the design are handled automatically with physically aware level shifter and isolation cell insertion along with automatic power grid synthesis and voltage domain-based optimization.
Completing the design flow is ARM’s Metro standard cell library, meant to allow rapid implementation of low-power designs with minimal manual intervention, and reducing time-to-market for power-sensitive SoC designs.
ARM recognizes that “a complete, low-power implementation solution is critical to our customers’ success,” according to Neal Carney, VP of marketing for physical IP at the company, in a statement. “By enabling Magma to develop a comprehensive low-power solution with our IP products, we are together ensuring the success of our mutual customers by enabling the rapid implementation and deployment of advanced, energy efficient IP."
Magma worked with customers for several years to develop this low-power design flow, to allow the power versus timing versus area tradeoffs throughout the low-power, 90nm and below RTL-to-GDSII flow according to Premal Buch, general manager of Magma’s design implementation business unit.
