National Semiconductor has introduced what’s said to be the industry’s first triple-rate (3G/HD/SD) serial digital interface (SDI) and video clocking daughter card development kits that maximize system performance and simplify the design of new broadcast video equipment. The two daughter cards are compatible with development kits from Altera and Xilinx and include synthesizable field-programmable gate array (FPGA) source code and the entire SDI signal path and video clocking solution together on one board. This allows designers to evaluate system performance, implement or modify FPGA source code, finalize architectures and start new designs.
Broadcast and professional video equipment designers now have a one-stop shop for beginning new, ultra-low jitter SDI designs for video routers, production switchers, video servers and a wide range of video editing and post-production equipment. Both daughter cards support industry-standard 270 Mbps, 1.485 Gbps and 2.97 Gbps data rates, enabling transmission of digital video broadcasting-asynchronous serial interface (DVB-ASI), standard-definition (SMPTE 259M-C), high-definition (SMPTE 292M) and the new 3G-SDI standard (SMPTE 424M) for uncompressed serial transmission of 1080p50/60 signals over a single link of coaxial cable.
SDALTEVK and SDXILEVK Daughter Cards/Development Kits
National’s SDALTEVK daughter card plugs directly into Altera's Cyclone III development board via a high-speed mezannine connector (HSMC), while the SDXILEVK daughter card plugs directly into the Xilinx Spartan-3A development board via Avnet's EXP expansion module. Each National daughter card supports a complete 3G-SDI signal path consisting of adaptive cable equalizer (LMH0344), deserializer with reclocked loop through (LMH0341) and serializer with integrated cable driver (LMH0340). A multi-rate sync separator (LMH1981) and clock generator (LMH1982) deliver ultra-low-jitter reference clocks to the host FPGA. A reference clock selector -- either 4 x 4 low-voltage differential signaling (LVDS) crosspoint switch (DS25CP104) or 2 x 2 LVDS crosspoint switch (DS90CP22) -- enables four selectable clocking options:
· Recovered clock from LMH0341 deserializer
· Genlock from analog reference, LMH1981 sync separator and LMH1982 clock generator
· Local clock generation from LMH1982 in free-run mode
· External clock via subminiature version-A (SMA) connector
These selectable reference clocks allow designers to quickly compare system jitter performance, using different clocking sources, and then select the best fit for their project. For example, one application may require genlock capability for synchronization while another one leverages the recovered clock from the SDI deserializer.
The daughter cards are independently powered by National’s LP3878 low-noise dropout regulator (LDO). The SDALTEVK includes National's PowerWise LM20242 adjustable-frequency synchronous buck regulator.
Each development kit includes FPGA IP for audio embedding and test pattern generation, plus framing for SD, HD and 3 Gbps type-A SDI formats. National provides both the hardware and FPGA firmware, enabling system designers to modify their design, quickly adapt to standard changes, add features and reduce time-to-market. Competing solutions that integrate the protocol blocks locally in the discrete SerDes constrain system designs to a fixed set of digital functions that limit flexibility and raise compatibility issues.
National Semiconductor
