Modern power-supply design presents a three-dimensional challenge to the designers:
· A power-handling section involving semiconductor switches, magnetic devices and capacitors, which necessarily remains in the exclusive analog domain
· An active-feedback control-loop section, which electrically manipulates the semiconductor switches to achieve high-efficiency voltage conversion and regulation
· Peripheral functions (such as voltage monitoring, sequencing, protection, etc.) that guide and protect the device or communicate with its environment.
Peripheral functions have long been within the scope of digital control, whereas the control of an active feedback loop, including a pulse-modulation process (the power converter “core”), remained analog for a long time. This is because digital control of power-converter operating characteristics requires data resolution and latency (path delay) numbers earlier available only in large, expensive DSP and Analog-to-Digital (A/D) converter products.
Recent advancements in Digital Signal Controllers (DSCs) that are tailored for SMPS applications has made it possible to implement fully-digital control of power-converters. In the case of a fully-digital control scheme, the power-converter operating characteristics are controlled by a stored program, rather than the parameters of a set of discrete components. Tremendous cost and space savings, as well as improved reliability are the direct results of a reduced number of discrete components. Greater sophistication in control algorithms further improves the performance, reliability and efficiency power-conversion systems. Control via reprogrammable software control also offers new, innovative features and greater product flexibility, at a lower cost.
DSC Architecture for Digital Power Conversion
A DSC has the look-and-feel of a microcontroller, with Digital Signal Processor (DSP) capabilities. The DSP portion of the DSC performs the basic math to implement the digital control algorithm. Figure 1 is a basic block diagram of an example DSC equipped with all the elements necessary for implementing a fully-digital control loop, as well as various peripheral functions. This DSC has a 16-bit, fixed-point, internal DSP engine.
The real innovation behind the SMPS dsPIC DSCs exists in the combination of their high-performance, onboard digital Pulse-Width-Modulation (PWM), ADC and analog comparator modules. These peripherals are collectively tied together by a configurable control fabric to form an Intelligent Power Peripheral, which provides the foundation to effectively perform digital-loop control.
The precision RC oscillator, internal Phase-Locked Loop circuits, onboard memory and communication peripherals are some of the other features that help to reduce part count and increase power-supply reliability.
In looking at digital power-conversion designs, designers must also consider the auxiliary power required for the control circuits and the DSC, itself. The DSC in Figure 1 has an onboard power-management subsystem that provides the power-on reset and the internal voltages required to enable a single-supply voltage to the DSC.
Implementing the Digital Loop inside a DSC
To implement the digital control loop, first the analog signals are converted to digital samples by an ADC, as shown in figure 2. The sample-and-hold (S&H) circuit associated with the ADC typically samples every 2 to 10 microseconds (µsec), and the ADC requires approximately 500 nanoseconds (ns) to convert the analog feedback signal to a digital value.
The Proportional, Integral, and Differential (PID) controller is a program that runs on the DSC with a computation delay of about 1 to 2 µsecs. The controller output is converted to a PWM signal, which drives the switching circuitry. The PWM generator can introduce significant delays if it cannot immediately update its output, when given a new duty-cycle. Additionally, the transistor drivers and associated transistors introduce delays from 50 ns to about 1 µsec, depending upon the devices used and the circuit’s design. The output filter, typically implemented with an inductor and capacitor circuit, can also cause significant delays.
In this example, the control delay is 4.1 ms, resulting in a raw sampling rate (inverse of the control delay) of approximately 244 kHz. In general, 6 to 10 times over sampling is required for loop stability. In this example, 6 times over sampling rate is needed to achieve the required performance of the loop—hence the estimated controller bandwidth is approximately 40 kHz. The addition of feed-forward terms to the control algorithm can increase the performance of the controller beyond the capabilities of a traditional PID controller with a 40 kHz bandwidth.
With this example in mind, let us see how implementing this basic loop drives some of the architecture requirements. To prevent the PWM ripple from affecting the controller, the PWM-reload frequency should be at least 4 or 5 times higher than the DSC’s bandwidth. Many power-converter applications generally use a PWM frequency as high as 500 kHz or more. Regardless of the PWM frequency selection, reliable implementation of a digital control loop may require around 1 ns PWM resolution. If a DSC’s digital PWM module does not have adequate resolution, the control system will dither its outputs to achieve the desired average output. This phenomenon is called “Limit Cycling” and creates problems with ripple currents.
The central “core” of the control software is the PID loop. The PID software is typically small – one or two pages of code – but its execution rate is very high – often hundreds of thousands of iterations per second!
This high iteration rate requires the PID software routine to be as efficient as possible for optimal performance. A PID loop, implemented in assembly language on a 30 MIPS dsPIC DSC, takes approximately 1 µsec to perform the loop. This is performed in an ADC interrupt service routine that requires five clock cycles to enter, and the software requires 27 clocks.
Digital power conversion applications require that the ADC samples the signals at precise locations that are set in relation to the driving signal from the PWM, as illustrated in Figure 3.
In this example, it is desirable to measure the peak inductor current that flows through the sense resistor R. The peak current occurs just as the transistor turns “off”. Triggering the ADC via PWM sate ensures best possible feedback for the control loop.
Additionally, multiple ADC S&H circuits are important, as they can be triggered asynchronously by different PWM pulses at different times. Multiple S&H circuits enable implementation of more than one asynchronous loop, often required to design power-conversion control.
Additional key peripherals are onboard analog comparators that are used to perform current limiting or fault shutdown of the digital PWM signals. These comparators should provide a fast response, and each comparator should have its own 10-bit DAC to enable the user to control the comparator’s threshold. Figure 4 shows a system example of using analog comparators to perform current limiting.
Typically, the time from when the analog voltage is sensed to when the comparator modifies the PWM output should be about 25 ns. This response time is far faster than what is possible via software “polling” techniques, which utilize the ADC and processor software to modify the PWM outputs in response to changing conditions.
AC-to-DC Power Supply
Figure 5 shows a block diagram of an AC-to-DC power supply, a practical example of a complex power product utilizing digital power-conversion techniques.
The design in Figure 5 is broken into three main sections -- boost PFC, Isolated DC-to-DC converter, and a set of low-voltage DC-to-DC synchronous buck converters. The AC-input voltage is converted to DC and boosted up to 400 VDC in the PFC circuit, which ensures that the current drawn from the power-line is sinusoidal in format and in phase with the line voltage. The digital PWM feature that supports the addition of PFC is an independent time base for the PWM complementary pairs.
This 400 VDC is then fed into a full-bridge DC-to-DC modulator circuit, which creates a pulsing voltage that can be applied to a transformer. The transformer provides isolation between the AC line and the DC-output voltages, as well as a voltage translation from 400 VDC to a lower voltage. The transformer’s output is then rectified and filtered to produce an intermediate-bus voltage, say 12 VDC. This intermediate-bus provides power to a set of Synchronous Buck converters to produce the final output voltages.
There are two DSCs used in this design – one controls the PFC and push-pull circuits, and the other controls the buck converters and provides feedback information to the primary-side DSC. The placement of the two DSCs in the system eliminates the need for the isolation of analog signals. The isolation can be limited to two digital signals used for serial communications between the processors, which can be inexpensively and reliably isolated. Of course, the DSCs in the system should be affordable and compact enough so that several of them can be used in one design, if necessary.
Flexible Digital PWM
To implement a variety of topologies, such as Push-Pull, Half-Bridge, Full-Bridge or H-bridge, and many other innovative switching techniques, the digital PWM onboard the DSC selected should be quite flexible. The PWM module should not only be configurable in any of the following modes, but also provide up to 1 ns resolution over all seven PWM modes:
Standard mode, where one or two outputs provide the same PWM waveforms.
Complementary mode, which provides a PWM-output signal on one pin and the complement of the PWM signal on the other output pin.
Push-Pull mode provides a standard PWM signal on one output pin. On the next cycle, the PWM signal outputs to the other pin, and then the process repeats.
Multi-Phase mode allows multiple PWM generators to output PWM signals that are synchronized, but phase-shifted, relative to each other.
Variable-Phase mode is similar to Multi-Phase mode, but the phase relationships are constantly changing.
Current-Reset mode is a variable-frequency mode where the user specifies an “on” time, and an external signal or an internal analog comparator truncates the “off” time.
Current-Limit mode, where an analog comparator or external signal truncates the digital PWM “on” time, on a cycle-by-cycle basis. This is known as cycle-by-cycle current limiting.
Conclusion
Digital power conversion is increasingly used in power-supply products to enable higher performance, efficiency and power density. This paper has reviewed practical tips that designers can use to achieve these goals, beginning with the selection of the appropriate hardware architecture.
Quite a bit of the value of using digital techniques is the freedom that it affords designers in creating and protecting new intellectual property (IP). Designers using new, flexible DSCs for digital power conversion are experiencing newfound abilities to innovative new topologies and algorithms. This new IP can be quickly and efficiently tested, as it is implemented in firmware rather than hardware.
Devices such as the dsPIC DSCs also feature CodeGuard Security, which enables designers to provide processor subsystems that house their firmware IP to end customers for further design customization.
Captions
Figure 1: Block Diagram of an Example DSC for Digital Power-Conversion
Figure 2: Example Fully-Digital SMPS Control System
Figure 3: Example of Asynchronous ADC Sampling
Figure 4: Current Limiting Using an Analog Comparator
Figure 5: Digital AC-to-DC Power Supply Block Diagram
Click here for the illustrations: Figure 1, Figure 2, Figure 3, Figure 4, Figure 5
