Rambus announced that Panasonic Corporation has licensed Rambus’ DDR3 memory controller interface solution for system LSI implementation in consumer electronics products. This fully-integrated macro cell architecture provides the physical layer (PHY) interface between the controller logic and DDR3 DRAM devices to achieve data rates up to 1.6Gbps.
To enable a reliable system environment for high-volume production and first-silicon success, the Rambus DDR3 memory architecture incorporates patented Rambus innovations such as FlexPhase™ timing adjustment circuits for precise on-chip data alignment with the clock, calibrated output drivers, and on-die termination.
Rambus interface solutions provide a comprehensive architecture and system design, as well as design models and integration tools. Included in the solution are reference GDSII database, timing models, layout verification netlists, gate-level models, place-and-route outline, and placement guidelines. Package design and system board layout services are also available. For more information about the Rambus DDR3 memory controller interface please visit www.rambus.com/ddr.
Rambus Inc., www.rambus.com.
