THE CHALLENGE
Today’s processors, graphics, and memory systems use multiple phase power solutions. These multi-phase solutions offer the responsiveness and regulation performance of a very high switching frequency converter, while individually switching at a much more modest frequency. They also can provide much higher output current than practical for a single buck converter. The advantage of multi-phase power supplies stems from the interleaving of the phases. By staggering the phases at uniform intervals (e.g., 120° in a three-phase interleaved converter), the inherent output ripple of each individual phase is averaged down by the other phases such that the total output ripple is reduced. This allows the use of lower pulse width modulation (PWM) switching frequencies for a given output ripple design goal, which in turn increases efficiency by reducing switching losses.
Managing a multi-phase power system presents its own set of challenges, including phase shedding for light load efficiency and system redundancy, and phase current balancing for system longevity. While implementing these features in a conventional analog power supply would be difficult, such tasks are easily handled using a digital controller. In this case study, a digital power solution is presented that provides the benefits of multiple phase synchronous buck converters, while closing the voltage control loop digitally and managing the phases for maximum power supply performance under various load and thermal conditions.
THE SOLUTION
The system consists of up to six interleaved synchronous buck converters controlled by a single microprocessor, as shown in Figure 1.
TI’s 32-bit TMS320F2806 digital signal controller (DSC) operates at 100 MHz and targets power supply applications. It implements voltage mode control in software using, in this example, a single 2-pole, 2-zero digital compensator sampling at the PWM switching frequency. The resulting duty cycle value is sent to each buck phase (excluding any duty adjustments made for phase balancing). System output voltage feedback is obtained using the on-chip 12-bit analog-to-digital converter (ADC). MOSFET temperatures are also available through the ADC for monitoring purposes, and the on-chip inter-integrated circuit (I2C) port provides support for PMBus communication. A UCD7230 gate driver is specifically designed for synchronous buck applications, providing dual 4-A MOSFET drivers using TI’s TrueDrive output architecture, cycle-by-cycle current limiting, and a built-in low offset, high-gain, differential current sense amplifier.
Phase Shedding and Adding
Phase shedding provides a means of increasing power supply efficiency and reliability. At light loads, dynamically reducing the number of operating phases often results in an efficiency increase. A shed phase can be re-activated when load demands increase. Similarly, shedding a phase that has suffered a failure or is operating in an out of bounds condition helps maintain performance by re-balancing the interleaving between the remaining phases. In applications requiring very high reliability, a spare phase can be brought on-line in place of the failed phase, i.e., N+1 redundancy. Regardless of the reason for shedding a phase, the interleaving angles of the remaining phases (or the added phase, in the case of N+1 redundancy) should be re-spaced to maintain peak performance. For example, shedding one phase from a three-phase, 120° interleaved converter results in two phases that should be spaced 180° apart.
The PWM units on the TMS320F2806 controller support software synchronization and phase control. Each PWM output has a phase synchronization register that offsets its count value from that of the first PWM output. This allows the phase angles of each interleaved buck phase to not only be statically configured during system initialization, but also dynamically re-adjusted during system operation.
Figure 2a shows an oscilloscope screen capture of a three-phase interleaved buck converter with the PWM configured for 120° interleaving (conditions: 10V input, 2V output, 3A load, 300 kHz PWM switching). Scope channels 1 to 3 show the individual phase voltages, while channel 4 shows the interleaved output voltage (all scope channels are AC coupled). With all three phases in operation, the output ripple is 4.9 mV (0.25 percent of the output voltage). Shedding phase 2 without adjusting the angles of the remaining two phases (Figure 2b) causes the output ripple to increase by 86 percent to 9.1 mV. After software adjustment of the remaining two phases for 180° interleaving (Figure 2c), the ripple reduces to 7.9 mV. While still higher than the original value (since a two-phase system cannot achieve as low a ripple as a three-phase system), it is a 13 percent improvement over leaving the phase angles unadjusted.
Phase Current Balancing:
To maximize power component reliability and longevity, it is desirable to have each phase in a multi-phase system handle an equal share of the power burden. Due to component-to-component variation in power switches and inductors, and asymmetries in board layout and thermal cooling, current flow through the phases will not be identical. The basic balancing approach involves measuring the phase currents and individually adjusting the PWM duty cycle commanded of each phase to equalize the currents. The current imbalance dynamics are quite slow, and thus the sample rate of the balancing loop can be low, on the order of tenths of seconds or even seconds. The additional computational burden on the microprocessor, therefore, is negligible. To reduce the effect of sensor noise, the current readings are oversampled with respect to the balancing loop rate, with each phase current measurement averaged over time. Simple low-gain, integral action only control algorithms are typically used to close the balancing loop. Balancing can be performed on every phase during each loop iteration using the average phase current as the reference. Alternately, sometimes only the highest and lowest current phases measured at that instant are balanced against each other. With either method, all phase currents will eventually converge to the same value.
PWM resolution is often an issue with phase current balancing. Consider a 10V input to 2V output synchronous buck converter driven by 300 kHz PWM from a 100 MHz PWM clock. The PWM resolution will be 30 mV on the buck output, or the equivalent of 1.5 percent of the 2V output. Generally, such granularity will be one or even two orders of magnitude greater than the fine duty cycle adjustments needed to achieve phase balance and avoid limit cycling in the balancing control loop. The F2806 controller gives a solution to this problem with unique high-resolution enhancements to the PWM modules. The high-resolution PWM provide ~150 ps edge positioning. This equates to 0.45 mV output resolution for the aforementioned buck example, or 0.02 percent of the 2V output. This resolution provides for precise and well behaved phase current balancing.
CONCLUSION
A digitally controlled multi-phase interleaved DC/DC buck system has been described that implements voltage-mode regulation control and features phase shedding and adding, and multi-phase current balancing. While implementing such features using a conventional analog controller would be quite challenging, a microprocessor-based digital controller easily lends itself to the task. The F2806 digital signal controller, combined with the gate drive and current sense amplifier of the UCD7230, provides a complete digital control solution, with on-chip flash memory for stand-alone operation, synchronized high-resolution PWM modules, an ADC for measuring feedback signals, and PMBus communication capabilities.
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