Atrenta Inc., a provider of Early Design Closure solutions to radically improve design efficiency throughout the IC design flow, kicked off its Design Closure Stimulus Package seminar series in India, starting Jan 29, 2009. A seminar entitled Catching CDC and DFT Bugs was held in Noida on Jan 28, 2009, and in Bangalore on Feb 2, 2009.
Experts from Atrenta, Dr. Shaker Sarwary and Kiran Vittal, presented informative, in-depth information and case studies detailing many important design challenges. The seminar addressed design issues such as interfacing and synchronizing of all the blocks in the chip, including third party IP, and managing multiple asynchronous clocks spanning different clock domains and verifying them accurately to achieve manufacturing test goals.
The seminars received overwhelming response and were attended by a total of 130 design engineers from leading semiconductor companies. The attendees walked away with vital insights into how to find dangerous and hard-to-find CDC and DFT bugs early to ensure that clock synchronizations are correct and test quality goals are achieved.
Design engineers, feeling the stringent cost cutting measures by semiconductor companies in these difficult economic times, were eager for information as the live question and answer section lasted several minutes. One of the attendees reported, "This seminar was extremely informative and I felt like all my questions were answered directly. I would definitely recommend this seminar to all my industry friends."
Earlier this year, Atrenta announced its Design Closure Stimulus Package seminar series. These seminars will assist chip companies to build better products, both faster and more economically, by detecting and mitigating design risks earlier in the design process than ever before. Atrenta will visit major semiconductor hubs around the world to share the latest technologies and methodologies for Early Design Closure. The Design Closure Stimulus Package Seminar Series will extend through 2009 and 2010.
Presented by the company’s technology experts, these seminars will be aimed primarily at engineering managers, chip architects, RTL designers, design methodology engineers and IP design/verification engineers seeking to implement correct designs rapidly through the integrated use of a variety of design automation solutions. The free seminars, typically scheduled for 90 to 120 minutes during lunch, will cover a variety of topics, including clock domain crossing verification, design for test, constraints analysis, power management, modeling of physical effects at RTL and platform-based design techniques. Detailed case studies will demonstrate how to improve methodologies and achieve better Early Design Closure.
