NEC Electronics Corp. (NECEL) has chosen Virage Logic Corp. to provide its comprehensive portfolio of silicon-proven Silicon Aware IP at the 40nm process node. The use of Virage Logic’s highly differentiated Silicon Aware IP helps enable IDMs like NECEL to design faster, lower-power and more area-efficient system-on-chips (SoCs) while achieving higher yields.
The SiWare Memory products provide a powerful dashboard that enables SoC designers to manage the tradeoffs between performance, area, power and statistical yield to generate optimal memory configurations. The ability to meet key design requirements is critical at 40nm where design and process complexities demand sophisticated management of the various tradeoffs to effectively meet stringent end-product requirements and increasingly narrow market windows.
“Integrated circuits targeting consumer applications demand lower power consumption and smaller form factors which are driving the adoption of advanced process technologies,” says Brani Buric, Executive Vice President of Marketing and Sales, Virage Logic. “By partnering with Virage Logic to gain access to highly differentiated IP for optimal performance, power, area and yield while achieving lower overall design and manufacturing costs, IDMs can help accelerate the delivery of a broad range of innovative products to the global market.”
Virage Logic has been serving as NECEL’s trusted IP partner since 2002 with its initial selection of Virage Logic’s 130nm Area, Speed and Power (ASAP) Memory and 150nm Non-Volatile Electrically Alterable (NOVeA) Memory products. The expanded relationship includes the use of Virage Logic’s SiWare Memory compilers and SiWare Logic libraries, and Self-Test and Repair (STAR) Memory System for NECEL’s 40nm SoC devices.
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