The world is facing phenomenal energy demand. At the same time, population growth, economic expansion and urban development is creating a greater demand for more personal-mobility items, appliances, devices and services. Recognizing these worrisome trends, the U.S. Department of Energy (DOE) has identified the reduction of energy consumption in commercial and residential buildings as a strategic goal. The Energy Information Administration at DOE attributed 33 percent of the primary energy consumption in the United States to building space heating and cooling—an amount equivalent to 2.1 billion barrels of oil. At these levels, even a modest increase in efficiency of heating ventilation and air conditioning (HVAC) and energy efficient equipments will provide direct economic benefits to people, enabling reduction and better management of electric utility grid demand. In addition to the global relevance of efficient energy usage, there are convenience concerns of users, where battery life of home mobile appliances is becoming a major selection factor for consumers. What can electronics makers do to help?
Power consumption in wireless consumer devices has become a key part of many product specifications. Even for wired devices, in which battery power has not traditionally been an issue, considerations of packaging, reliability, and cooling costs bring power to the forefront. More than ever, designers are recognizing the impact of power consumption on IC performance. In every application, power management must take precedence, whether to reduce energy use, or to minimize heat dissipation to lower cooling and packaging costs. Power consumption grows exponentially at sub-90nm. Voltage cannot scale indefinitely, and capacitance—dominated by more wires with higher wire capacitance—increases, while frequency keeps going up. Ineffective power management decreases battery life, lowers chip performance, increases area due to cooling needs, or simply makes the design nonfunctional. Leakage power now dominates 90nm and below devices, and high power consumption imposes ever more severe heat and performance penalties.
How are designers going to cope with the new challenges of power management? Given the increasing complexity of designs, power can no longer be considered an afterthought. Traditional methodologies address power only after the chip’s timing and area goals are met. But power must now be considered concurrently with timing and area. Moreover, power optimization should be a conscious effort, from synthesis through the final implementation of the flow. Therefore, one must rethink chip design methodologies that traditionally didn't consider power reduction as a critical requirement.
Energy usage can be optimized at the chip, board, box, system, and network level. At each of these levels there are major gains that can be achieved. Low-power design has been a substantial research theme for years in IC design. Several important results have been used to limit energy consumption by fast components such as microprocessors and digital signal processors. However, while the trend has been improving, the energy consumption of processors warrants additional research. As we traverse layers of abstractions towards systems and networks, the attention paid to low energy consumption is not increasing proportionally; an important issue to consider moving forward on the energy conservation path. As designs migrate to sub-90nm process nodes, power management becomes a serious concern across the entire design and manufacturing chain. To achieve required power targets, design teams must adopt advanced power management techniques such as multi-supply multi-voltage (MSMV), dynamic voltage and frequency scaling (DVFS), and power shutoff (PSO). Such techniques, however, increase design complexity and introduce risk. Conventional design flows fail to address the additional considerations for incorporating advanced low-power design techniques. Consequently, design teams often resort to ad hoc or inflexible methodologies that result in lower productivity, increased risk of silicon failure, longer time to market, and inferior product performance.
A NEW POWER STRATEGY FOR THE BEST QOSPower needs to be considered at the very early stages of a design, when the opportunity to save power is at a maximum. At the same time, making a design extremely power-efficient results in trading off area and/or timing. A balanced approach is warranted when it comes to power optimization that spans across the entire RTL-to-GDS flow.
Two aspects of “power awareness” are essential for effective designs that minimize power consumption—the level of abstraction, and Quality of Silicon (QoS). The higher the level of abstraction when power is taken into account, the greater the power efficiency that can be gained, because there is more freedom to make large changes to the design implementation. New system and architecture designs can yield implementations that are 10 to 20 times more power efficient than previous designs, so optimization and analysis of power early in the design process, at high levels of abstraction, are critical (Figure 1).
QoS is becoming the new standard for evaluation of the “goodness” of an IC design because this measurement requires placement and routed wires that account for the majority of the timing equation in nanometer designs. QoS measurements include speed (timing of the performance limiting paths), die area, and power. The power portion of QoS measurements consists of the static and dynamic power consumption determined using real wires. As QoS is fast becoming the metric for an entire design, a holistic set of tools is required so designers can gain a better understanding of power/area/performance tradeoffs, and come up with the most effective balance for each individual design.
Figure 2 provides a rough idea of the power reductions available from various techniques, along with the timing/area tradeoffs and their potential methodology impact. In general, there's a tradeoff between the amount of power reduction you can expect and the amount of work needed to apply the techniques. The challenge for designers is choosing the most suitable power-management techniques that deliver the target QoS while minimizing the cost and risk associated with methodology changes.
As an example, the following techniques can be added to the traditional design flow without fundamentally changing the way the tools work:
• Global concurrent optimization of timing, area, and power
• Leakage optimization methods, including multi-VT synthesis
• Hierarchical clock gating
• Low-power clock-tree synthesis
All of these techniques are useful, and the list could be even longer, including a number of other well-understood techniques that involve minimal tradeoffs for designers. Techniques such as pin swapping, operand isolation, and toggle-rate reduction may be easy to implement, but they have minimal impact on power.
INTEGRATED SOLUTIONDesigners are looking to different sources for reduction of power consumption, and will ultimately see that the solutions are required in all stages of the design. An effective power management flow would need to attack the issues in a top-down fashion, from the highest opportunity—which is in the RTL synthesis and gate optimization—to the implementation phase, and finally the validation of design integrity. The seemingly complex solutions, however, need to be cohesively thought out, so that the best QoS can be achieved and be easily applicable to reduce barriers to efficient design. Figure 3 shows the low-power design flow which addresses the power management issue with multilevel solutions throughout the design flow.
Advanced process technology is in place, power reduction techniques are being known, but design automation and its infrastructure is also needed. Low-power design flows needs to be automated—manual flows being error-prone, risky, and expensive. The pressure to reduce power is ever more pervasive and the methodologies available were undesirable. Across the design and manufacturing chain, an urgent need has emerged for an automated, power-aware design infrastructure. To facilitate and support a new era of low-power design innovation, there is a need for collaboration across the industry.
Drawing from the collective expertise of leading technology companies, the Power Forward Initiative creates a more systematic, integrated approach to low-power design, providing a platform for higher-level exploration and IP reuse. Power Forward Initiative members worked on validating the Common Power Format (CPF), a new open specification language that captures all power-specific design, constraint, and functionality requirements, such as multi-supply voltage and power shutoff, in a single file. This initiative combines a variety of low power technologies that leverage the Si2 CPF—which specifies power-saving techniques early in the design process—enabling design teams to share and reuse low-power intelligence. The power intent for the full chip can be effectively captured using the CPF. Advanced low-power SoC design tools support the low-power intent captured in the CPF commands.
By linking design, verification, and implementation domains, the CPF enables automation of power-reduction techniques and increases predictability. No longer constrained by the risk of low yield or costly re-spins, design teams can focus their time and resources on what matters most—innovation. Achieving both functional and structural verification before incurring manufacturing costs, and with greater time-to-market opportunities, companies across the design and manufacturing chain can adopt new process geometries and start low-power design projects profitably.
The CPF-enabled Low-power Solution does the following:
• Reduces risk: By minimizing the need for manual intervention and using a robust verification methodology, design teams can eliminate silicon failure risks that stem from functional and structural flaws.
• Boosts productivity and speeds time to market: With integrated logic design, verification, and implementation technologies, design teams maintain high productivity levels. By reducing the number of iterations within the flow and limiting silicon re-spins, design teams can predictably address time-to-market concerns.
• Increases quality of silicon: Through easy-to-use “what-if” exploration early in the flow, designers can identify optimal power architectures to achieve desired specifications. Subsequently, optimization engines in the implementation flow help achieve superior tradeoff among timing, power, and area targets.
CAPTIONS
Figure 1: Power consumption savings at various stages of the design.
Figure 2: Various power reduction techniques along with timing/area impact.
Figure 3: Complete low power design flow.
Figure 4: CPF-enabled low power flow; power is connected.
