Cadence Design Systems Inc.’s latest innovative, scalable co-design solution for designing FPGAs onto PCB systems—the Cadence OrCAD and Allegro FPGA System Planner—shortens time to design in today’s complex FPGAs while reducing risk by delivering an automated placement-aware FPGA pin I/O assignment synthesis.
Developed by Taray Inc. and available to Cadence customers through an OEM agreement, this exclusive joint solution offers an optimized correct-by-construction FPGA pin assignment that reduces the number of pin optimization iterations during PCB layout while reducing the number of layers required to route the FPGA on a PCB design. Allegro FPGA System Planner also shortens time for companies using FPGAs on PCB systems to emulate their ASICs through automated FPGA pin assignment.
The technology is available in a series of scalable solutions from the OrCAD FPGA System Planner to the Allegro FPGA System Planner L, XL and GXL tiers, and is tightly integrated with OrCAD Capture, OrCAD PCB Designer, Allegro Design Entry HDL and Allegro PCB Design products. The FPGA System Planner shortens the time it takes to integrate FPGAs on a PCB, enhances FPGA performance through the optimal utilization of FPGA resources, and can reduce PCB manufacturing costs through the reduction in the number of PCB layers required to route dense, complex, large pin-count FPGAs.
OrCAD and Allegro FPGA System Planner
Cadence
