Mentor Graphics Corp. has launched the Olympus-SoC platform, its latest place-and-route solution that enables low power IC implementation and is targeted for advanced technology processes. Featuring production-proven design-for-variability architecture that natively optimizes for variations in design modes, process corners and manufacturing, the Olympus-SoC provides customers two to three times faster design closure times, as well as up to 30 percent power savings versus traditional solutions.
The Olympus-SoC low power place-and-route platform includes a flexible architecture for automated multi-voltage design flow, and advanced techniques for power reduction in complex clock trees. It also includes concurrent optimization of leakage and dynamic power, timing and signal integrity across multi-corner multi-mode (MCMM) scenarios. It comprehensively handles the requirements of low-power design, while ensuring optimization of the overall solution without excessive design iterations. The system features completely automated multi-voltage flow with support for Dynamic Voltage and Frequency Scaling (DVFS) to handle varying supply voltages and clock frequencies, and the capability to handle special cells such as level shifters and isolation cells.
It also has power-aware CTS with smart clock gate placement, slew shaping, register clumping and concurrent MCMM optimization that ensures a balanced clock tree with the minimum number of clock buffers. The Olympus-SoC also has a Unified Power Format (UPF)-based Netlist-to-GDSII flow including support for power state definition tables.
Mentor Graphics Corp.
