India has established itself as a key resource for semiconductor design targeted at advanced process nodes. All the global top 10 fabless design companies and 19 of the top 25 semiconductor companies have operations in India. Keeping pace with the industry’s moves to smaller process nodes, many of these design houses in India are well past the 90nm mark, and have already completed 65nm and 45nm tapeouts.
ACHIEVING SMALLER DIE SIZEMoving to advanced process nodes has significant advantages and associated challenges. The biggest advantage is reducing die size which reduces costs. For example, a very prominent design house in Bangalore targets their 45nm designs to be 50 percent smaller than the corresponding 65nm variants. They have successfully used Talus Vortex, the integrated physical implementation solution provided by Magma Design Automation, for both their 65nm and 45nm tapeouts. While a 45nm device is smaller than the corresponding 65nm device by construction, this design house takes additional steps to further reduce die size.
First, their standard-cell design teams create smaller drive cells for the libraries. Using Magma’s integrated physical design solution for their physical implementation, they see close to 50 percent of the design using these smaller drive cells. Such a predominant use of these cells has an area benefit but also brings in other challenges. But the integrated flow provided by Magma is well suited to tackle these challenges.
Using these small cells significantly increases the pin-density (number of pins to be accessed per square millimeter), which makes it even more difficult for the software to route these layouts. An integrated physical implementation system has a unique advantage here because it uses the same global router throughout the flow from the initial placement stage to the final routing stage. This enables the designers to reliably predict the routing congestion of the designs at a very early stage and take corrective action upfront.
Because these smaller drive cells are extremely sensitive to load changes, it becomes very important to limit and maintain the RC loads on these cells throughout the flow. Using the built-in RC extractor of the integrated physical design system, this customer is able to get very good correlation between the RC estimates earlier in the flow and the actual RCs post layout, and this helps in managing the loads driven by these cells.
Second, this customer targets very high standard-cell densities during the physical design stage. For their latest 45nm tapeout, they were able to achieve >70 percent standard-cell utilization. Even with such high cell utilization, this design team was able to quite easily route the design using the integrated physical implementation solution.
MANAGING CROSSTALKThe next biggest challenge of moving to a smaller process node is handling crosstalk due to coupling (Fig 1). Unlike processes at 130 nm and above, where crosstalk induced delay and noise effects could be easily tackled as a post-processing measure, in the 65nm and 45nm designs it is mandatory to take preventive action upfront in the design flow to handle crosstalk.
For their last 45nm design, this design-house maintained very tight slew/transition characteristics throughout the design. Drivers with bad slews are the ones most prone to becoming crosstalk victims, and by keeping a tight control on the slews they were able to drastically reduce the number of aggressor-victim coupling relationships. However, at these advanced process nodes, there are still cases in the layout where a wire becomes a victim in spite of good slews. In such situations, some aggressive timing and crosstalk optimization is required post-layout, before going into sign-off.
This is where another challenge arises. For this customer, a flat 1.5-million- to 2-million-cell design is quite commonplace. Performing timing and optimization on such large designs while considering all crosstalk effects can be quite runtime intensive. The comprehensive multi-threading capabilities of the integrated physical design environment are particularly useful here. This customer is able to use state-of-the-art multi-CPU machines to completely multi-thread the timing, extraction and optimization of large designs, getting a runtime scaling anywhere between 2.5x to 4x. This enables the customer to close timing on huge designs very quickly before making the final dash towards tapeout.
Crosstalk on the clock network can exponentially increase timing closure problems in the design. This design team uses a variety of preventive techniques to make their clock trees highly immune to crosstalk. Their designs have very complex clocking structures. The highly customizable clock-tree-synthesis, along with the crosstalk-prevention techniques available inside the integrated physical design environment comes in very handy to create clock tree networks that meet their tight insertion-delay and skew requirements, and are highly immune to crosstalk.
MANAGING POWERWith die-sizes getting smaller and functionality per square millimeter getting higher, controlling the power consumption and power distribution becomes another challenge in 65nm and 45nm technologies. To address this, the customer follows a multi-pronged approach.
First, since the crowbar or short-circuit power is a significant contributor to the dynamic power consumed by the design, tight slew control, as mentioned earlier, indirectly solves this problem. The lesser the slews, the smaller the short-circuit time when both the PMOS and NMOS are active simultaneously, and hence the smaller the dynamic power loss.
Second, a fraction of the available standard-cell area is reserved for decap cells. These cells have no logical functionality and their sole purpose is to boost the power network during spikes of high local power consumption by releasing the capacitive charge stored inside them (Fig 2)
Most library vendors now provide multiple leakage variants of the standard cells. Magma’s integrated physical implementation solution provides a comprehensive multi-VT optimization flow, which can make the most optimal trade-off between high-leakage/high-speed cells and low-leakage/low-speed cells to concurrently achieve the timing, area and leakage targets of today’s designs.
MANAGING PROCESS VARIATIONMoving to smaller process nodes also brings in a totally new variable, namely, the need to time and optimize the design across multiple process corners, and thereby account for possible variation in device behavior and RC characteristics. At 130nm and above, it would suffice to ensure that the design meets its timing goals at the worst and the best process corners. However, at 65nm and 45nm, it is quite common for the design to meet its timing goals for the worst and the best corners, but still have violations in the intermediate corners.
This necessitates timing and optimizing the design across most, if not all, of the process corners supplied by the technology vendor. To further complicate the situation, the designs done at this wireless design company have multiple modes of operation, all of which need to be timed at these process corners. The concurrent multi-corner/multi-mode optimization feature of Magma’s integrated physical implementation solution is designed specifically for such situations, and has been successfully used by this design house to concurrently analyze and fix their setup and hold violations across these process corners and design modes in their recent 45nm tapeout.
This particular design company, and many others, have already reaped the benefits of moving to smaller technologies, and are pushing the envelope even further to 28nm. The vast and varied talent pool and state-of-the-art software and methodologies available in India are well suited to take on the challenges and opportunities arising out of this incessant drive towards advanced process nodes.
About the authorArpan Sircar is Technical Account Manager for Magma Design Automation. He can be reached at arpan@magma-da.com.
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