Gennum Corp.’s Snowbush IP group has developed what is said to be the industry’s first available integrated PCI Express 3.0 (Gen 3) PHY and Controller IP solution. The new PCIe 3.0 cores can be licensed immediately by system-on-a-chip (SoC) and system companies, enabling early deployment of PCIe 3.0 (Gen 3) in systems requiring the 8GTps performance of this new PCI-SIG standard. PCIe 3.0 opens up more bandwidth using the same physical connectors and adds new features to improve the user experience in server network and computer products using PCI Express.
The new Snowbush PCIe 3.0 IP is architected for low power and area on both the PHY and Data Link layer, and features low power consumption from a proprietary 5-tap Decision Feedback Equalization (DFE) and H-bridge transmit driver. The PHY silicon footprint is small and includes the I/Os, ESD structures, and PCS Layer, in 1-, 2-, 3-, and 4-lane configurations to reduce silicon cost. Each lane of the PHY can be configured to operate in Gen 1, Gen 2, or Gen 3 mode. Multiple 4-lane PHYs can be configured as x8, x16, x32, and greater links. An on-chip Fractional-N PLL Frequency Synthesizer with integrated Spread Spectrum Clocking is used for simplified external clocking and reduced SoC complexity.
The Controller features a low latency pipelined architecture that achieves industry-leading throughput. Available as an Endpoint, Root, Dual Mode, and Switch for x1, x4, x8, and x16 lane configurations the digital controller can be targeted for any application of PCI Express. The Controller’s micro and macro power options deliver a low energy profile that compliments the PHY layer’s low power consumption, together providing industry-leading thin power characteristics for mobile-based SoCs requiring PCI Express.
The integrated Snowbush device PHY and Controller solution satisfies the 8GTps speed requirement of PCIe 3.0, and exceeds the anticipated critical specifications for jitter performance over harsh channels on the PHY side. Low latency and power requirements in the link layer provide substantial margin to designers for creating robust products with excellent interoperability.
The new Snowbush PHY IP block employs a variety of techniques to ensure superior performance, reduced jitter and maximum noise immunity, including:
• A proprietary dual-loop hybrid clock-and-data recovery (CDR) architecture which recovers the clock with less jitter
• A coupled ring oscillator VCO design with jitter performance usually only found in complex LC tank oscillators
• Internal voltage and current regulation for sensitive circuits
• Fully differential circuitry and clock signaling
• Extensive use of guard rings within the macro
The new Controller IP block features:
• Atomic Operation (FetchAdd, Swap, Compare and Swap (CAS))
• Address translation services
• Transaction-Layer Processing Hints (TPH)
• 5GTps and 8GTps speed negotiation
• Optional and Mandatory Power Management Features
The new cores join a full suite of high-speed IP solutions that currently include PHY and controller products supporting the PCI Express 1.x, and 2.0, Serial ATA (SATA) 1.5Gbps, 3Gbps and 6Gbps, Fibre Channel and other high-speed standards requiring data rates from 5Gbps to 10Gbps data rates and beyond.
Gennum Snowbush IP Group
Gennum
