Synopsys Inc. and Semiconductor Manufacturing International Corp. (SMIC) have announced the availability of the 65nm RTL-to-GDSII reference design flow, version 4.0. The reference flow, the result of collaboration between Synopsys Professional Services and SMIC, adds the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology, expanding the resources available to designers to address low power and design-for-manufacturing challenges at smaller process nodes. The result for customers is immediate access to an optimized path to SMIC silicon at 65nm to help them meet aggressive project timelines.
The flow utilizes Synopsys' Galaxy Implementation Platform, a key part of the Eclypse Low Power Solution, providing designers with the ability to implement advanced low power techniques throughout the design flow including RTL synthesis and test, physical implementation and signoff stages. In addition, IC Compiler's Zroute technology supports SMIC's 65nm routing rules using advanced routing algorithms to evaluate the impact of manufacturing rules, timing and other design goals. The integration of Zroute balances design-for-manufacturing (DFM) optimization techniques with design timing, area, power and signal integrity goals for a particular chip design.
The reference design flow was validated using SMIC's in-house-developed CCS standard cell library, SRAM, PLL, IO Library and low power cell library. The validation included multiple Vdd and multiple supply blocks with power-gating and data retention. Additional key features of the flow include multi-corner multi-mode (MCMM) optimization and critical area analysis and reduction, using IC Compiler, and design-for-test (DFT) synthesis combined with on-chip clocking control support for automatic generation of at-speed tests.
SMIC
Synopsys
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