Rambus Inc. has showcased a silicon demonstration of a complete XDR memory system running at data rates up to 7.2Gbps with superior power efficiency. This silicon demonstration consists of Elpida’s recently-announced 1Gb XDR DRAM device and an XIO memory controller transmitting realistic data patterns. The XIO memory controller is up to 3.5 times more power efficient than a GDDR5 controller, and the total memory system can provide up to two times more bandwidth than GDDR5 at equivalent power. In addition, the XIO memory controller demonstrated bi-modal operation with support for both XDR DRAM as well as next-generation XDR2 DRAM.
This silicon demonstration, shown at Denali MemCon 2009 in San Jose, California, is the first implementation supporting the XDR memory architecture roadmap incorporating innovations developed as part of Rambus’ Terabyte Bandwidth Initiative. Implemented in the bi-modal XIO memory controller for XDR2 operation, these innovations include:
• Fully Differential Memory Architecture (FDMA) – enhances signal integrity and increases performance through point-to-point differential signaling of clock, data, and command/address (C/A), an industry first;
• FlexLink C/A – reduces pin count and increases scalability; and,
• Enhanced FlexPhase – enables the world’s highest memory signaling rates while simplifying routing and board design.
In addition, the XDR2 memory architecture includes:
• Micro-threading of the DRAM core – introduced by Rambus in early 2005, increases data transfer efficiency and reduces power consumption; and
• 16X Data Rate – allows for extremely high data rates with the use of a relatively low-speed system clock.
Built on these innovations, an XDR2 memory system can provide memory bandwidths of over 500GBps to an SoC. A single 4B-wide, 9.6Gbps XDR2 DRAM device can deliver up to 38.4GBps of peak bandwidth, and the XDR2 architecture supports a roadmap to device bandwidths of over 50GBps.
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