Renesas Technology Corp. has developed a SiP Top-Down Design Environment that boosts efficiency when developing system-in-package (SiP) products combining multiple chips, such as system-on-chip (SoC) devices, MCUs, and memories, in a single package. It uses a top-down (predictive) design approach in which key characteristics, such as design quality and heat dispersion, are verified during the initial design stage.
The SiP Top-Down Design Environment integrates and optimizes a variety of tools, including a database of information on chips that can be incorporated in SiP products and a substrate layout tool. It provides a common user interface that enables transfer of data between design tools, enhancing their ease of use and flexibility, and delivers a design environment that automates tasks such as analysis during circuit simulations. These advances allow steps that have a big impact on the amount of time required to develop a new SiP, such as analysis of electrical characteristics to ensure signal integrity and thermal analysis of heat dispersion characteristics, to be implemented during the initial design stage. Design quality is enhanced while development time is cut in half.
The SiP Top-Down Design Environment uses an integrated design database to provide unified management of design data and easy connections for analysis of electrical or heat dissipation characteristics. Thus, data on chip shapes and positions as well as chip-to-chip connection data can be extracted from the database and connected to the substrate layout tool. In turn, wire bonding and substrate pattern data from the substrate layout tool can be connected to other analysis tools. For enhanced ease of use, a common interface is provided for running the tools and making settings. It also includes an electromagnetic field analysis tool that supports large-scale substrates.
The new design environment extracts from the substrate layout data information on the conductor pattern area share (copper ratio), layer thickness, and materials of the internal SiP package wiring, power plane, etc., the number of via holes between layers, and the shapes and positions of the chips, and it automatically builds an environment for the heat dispersion evaluation package model. Another newly developed function applies the power consumption distribution of the SoC to the thermal analysis model so that the distribution of heat generation within the chips is taken into account. These advances not only increase the accuracy of the models, they make it possible to complete the thermal analysis in a short amount of time.
Renesas Technology Hong Kong
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