Altera Corp.'s 40nm Arria II GX FPGAs are now compliant with the PCI Express (PCIe) 2.0 specification. The device successfully passed the PCI-SIG Compliance and Interoperability Tests at the PCI-SIG Workshop and is now included on the PCI-SIG Integrators List. Arria II GX FPGAs achieved compliance for up to x8 lane configurations for PCIe Gen1 end-point applications.
Currently shipping, Altera's mid-range Arria II GX FPGAs feature integrated transceivers with data rates up to 3.75Gbps, and have a hard, configurable PCIe interface embedded within the device. The device's hard IP block implements PCIe Gen1 (PIPE) PHY-MAC, data link, and transaction layers. This IP block is highly configurable to meet the requirements to support end-point and root-port applications, and is PCIe 2.0 compliant in x1-, x4- and x8-lane configurations.
"Arria II GX FPGAs are the only mid-range FPGAs that have attained PCIe 2.0 compliance," said Luanne Schirrmeister, Senior Director of Component Product Marketing at Altera. "They offer 25 percent higher performance, up to 50 percent lower price and up to 50 percent lower power compared to competitive FPGAs."
Arria II GX FPGAs are targeted for applications using mainstream protocols such as PCIe and Gigabit Ethernet (GbE). The devices have up to 16 3.75Gbps transceivers, 256K logic elements (LEs) and 8.5Mb of internal RAM.
Altera's Arria II GX FPGAs
PCIe capabilities in Arria II GX FPGAs
Altera
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