Freescale’s MPC8569E communications processor, which targets wireless-access-infrastructure applications, expands the integrated QUICC (quad-integrated-communications-controller)-engine family of devices to processing support with as many as four internal RISC-processor engines, double the amount of RISC processing on previous QUICC devices. The devices maintain typical power consumption of less than 7 and 10W for the 800-MHz and 1.33-GHz cores, respectively. The QUICC engine block offloads datapath tasks from the e500 core to handle termination, interworking, and switching between communication protocols and interface standards, such as GbE (gigabit Ethernet), ATM (asynchronous transfer mode), HDLC (high-level data-link control), POS (packet over synchronous optical network), PPP (point-to-point protocol) and PWE3 (pseudowire emulation edge to edge). The QUICC engine sports as much as 256 kbytes of instruction RAM and 128 kbytes of multiuser RAM and can operate as fast as 667 MHz to support as many as eight 10/100-Mbps or four 10/100/1000-Mpbs Ethernet ports.
The e500 core operates as fast as 1.33 GHz and includes 32-kbyte instruction and data caches as well as a 512-kbyte L2 cache with ECC (error-correcting code). It includes support to access one 64-bit or two 32-bit DDR2/DDR3-memory interfaces with ECC, and the core supports double-precision floating-point operations. The integrated security engine supports ARC4 (alleged Rivest Cipher 4), 3DES (triple data-encryption standard), AES (advanced encryption standard), RSA/ECC (Rivest, Shamir, & Adleman/elliptic-curve cryptography), RNG (random-number generator), XOR (exclusive or), single-pass SSL/TLS (secure sockets layer/transport-layer security), Kasumi, and SNOW (scalable network of workstations). Other integrated features include an 800-Mbps/pin data rate, a 16-bit local bus for SRAM/flash memory, full-speed USB 2.0, high-speed serial interfaces, dual SGMII (serial gigabit media-independent interface), and dual one-lane Serial RapidIO or PCIe (peripheral-component-interconnect-express) interfaces. The integrated scalable SERDES (serializer/deserializer) interconnect helps to reduce system cost. These integrated features allow designs to replace separate control-path and datapath processors with a single device.
The MPC8569E is software-compatible with Freescale’s other PowerQUICC and QorIQ devices. The MPC8569E processor supports downloadable RAM-microcode packages that offer support for new functions or protocols. Freescale offers a modular-development system and a version of its CodeWarrior development environment for QUICC technology. Third-party vendors work with Freescale to offer RTOS support, compilers, debuggers, simulators, reference designs, and custom microcode for the MPC8569E family. The MPC8569E processor is available for sampling now, and prices begin at $80 (10,000).
Freescale Semiconductor
www.freescale.com
Caption
The MPC8569E communications processor targets wireless-access infrastructure applications and expands the integrated QUICC-engine family with as many as four internal RISC processor engines, double the amount on previous QUICC devices.
