From designing a wireless application to the latest consumer electronics product, power is now an important consideration in almost all designs. Power consumption significantly impacts the ability to differentiate a product based on features, cost, performance, time-to-market, and even reliability. As designs utilize sub-90nm process nodes, power management becomes a serious concern across the entire design and manufacturing chain. According to the ISA Frost and Sullivan report 2008, the Indian semiconductor market is poised to grow to $7.59 billion from $6.72 billion in 2009. The biggest growth drivers, according to the report, are the wireless and consumer electronics segments. Interestingly, for both these growth segments, consumers expect their devices to consume low power. With India rated as the fastest growing telecom market, it is imperative for any designer to consider power as a key design constraint.
CHALLENGESWith this shift in focus, power has joined the traditional constraints of timing and area. This means that a successful design environment and design methodology must simultaneously consider all design constraints (including power) in a seamless closed-loop, multi-objective planning-to-signoff solution. Addressing these needs is essential, regardless the types of power control design techniques that are being applied: basic power control techniques such as the use of multi-VT libraries or clock gating; more advanced techniques, such as dynamic voltage/frequency scaling or power shut-off; or emerging techniques, such as back-bias or low-swing clocks.
The risks of disregarding power trade-offs are high for project teams. In the extremely complex design of microelectronic circuits, the problem of estimating the effects of different design alternatives on the power dissipation arises. Design decisions made in a very early phase of the development process, in which the design consists of very abstract description (algorithmic level), have the greatest influence on the power dissipation.
To mitigate the formidable challenges of low power design, designers need a complete methodology for design-to-signoff that begins with early design planning, and includes front-end design, synthesis and physical implementation that ensures that consistency and convergence are achieved. This comprehensive flow should include power estimation and analysis at every step, software optimization, RTL synthesis and signoff. On the verification front, power-aware verification needs to be utilized throughout, leveraging static, dynamic, and formal power verification techniques in a closed-loop verification methodology.
At the architectural level, identifying the best-in-class IP’s, deciding on the optimized gating structure to minimize unwanted switching, developing power aware random logic, choosing the right set of low power libraries, and understanding the impact of multiple power modes in the chip is critical.
The ideal way to address these issues is to better formulate the power intent at the system and chip level. By allowing rapid exploration and options for “what-if” power analysis, teams have a better understanding of power trade-offs.
ARCHITECTURAL/PRE-RTL LEVEL POWER ESTIMATIONThere are software solutions available that provide IC design teams, architects and management with the ability to visualize tradeoffs throughout the chip design cycle. Bringing IP and manufacturing data to bear on the earliest stage of chip planning, this enables earlier and more informed decision-making in the context of critical decisions affecting chip performance, functionality and cost. The system helps users explore a wide range of chip architecture options in literally seconds including selection of IP, technology nodes and manufacturing technologies, low power strategies, packaging and much more. It also helps develop and optimize chip specifications gives accurate insight into chip size, power, leakage, performance and cost, as estimation results typically correlate well with final silicon.
Designers are able to get a preliminary estimation, based on the switching activity and clock gating factors. The rich library of IP’s and different technology node options within the infrastructure allows the user to seamlessly predict various options dynamically.
Using software such as Incyte Chip Estimator, power estimation can be done in different states (DeepSleep/Tx/Rx/Idle), for example in a wireless application. This allows a very early analysis of power consumption in the design across multiple states and modes of the chip. Users can perform a rapid “what-if” analysis on power consumption to compare their design across technology nodes, processes, IP options, and varying chip specifications.
RTL-LEVEL POWER ESTIMATION - DYNAMIC POWER ANALYSISEstimating low power with just the hardware component is not accurate; you need to consider the software entity as well. Software running on the chip has a significant effect on the amount of power it consumes. Software developers have to be fully aware of the low-power features that hardware developers build into chips, and write software that takes advantage of these features, while avoiding tasks and functions that might disrupt them.
Designers are looking for a dynamic power analysis solution that delivers superior productivity, increased predictability, and reduced risk. It should be able to run hardware/software “what-if” scenarios and adjust the design mid-stream without harsh consequences to the overall schedule.
Dynamic Power Analysis technology offerings have the ability to intelligently identify true peaks and average power based on switching activity in complex SoC designs and offers analysis capabilities through automation. It enables architects and designers to keep up with the ever increasing demands of balancing performance and power in an applications-hungry world. It provides a compelling bridge between the chip and software design worlds, ensuring that engineers in both disciplines can communicate and take advantage of advanced power management technologies.
CONCLUSIONToday optimizing energy consumption and low power designs are key issues for SoC designers, especially at advanced nodes. Designers want to explore the area, timing and power requirements for their design very early in the design cycle so that they can make the required adjustments. With shrinking geometries and increasing functional complexities, power management has become a critical component of product design at the system, architecture and RTL levels. Powerful EDA technologies are critical in helping designers and architects achieve their power goals.
ACKNOWLEDGMENTThe author would like to thank his colleagues Naresh Ramachandran, Bodhisatya Sarker, Mohan Subramaniam, Ajay Goyal and Maulik Patel for their contributions to this article. He can be contacted at arya@cadence.com.
