45nm TV system-on-chip

NXP’s TV550 is a new global DTV platform that brings key features such as H.264, HD ME/MC, CI+ and IPTV to mainstream TVs. To enable this functionality, NXP integrated an unparalleled number of complex IP blocks in an extremely efficient 45nm SoC.

The TV550 combines front-end video processing functions, such as DVB-T channel decoding for terrestrial broadcasts, MPEG-2/H.264 decoding, analog video decoding and HDMI reception, with advanced back-end video picture improvements. It also includes next generation Motion Accurate Picture Processing (MAPP2) technology, which provides state-of-the-art motion artifact reduction with movie judder cancellation, motion sharpness and vivid color management. High flat panel screen resolutions and refresh rates are supported with formats including 1,366×768 at 100Hz/120Hz and 1,920×1,080 at 100Hz/120Hz. The combination of Ethernet, CI+ and H.264 opens many possibilities for new TV experiences with IPTV or VOD. On top of that, optional support is available for 2D dimming in combination with LED backlights for optimum contrast and power savings of up to 50 percent.


Key features of the device include:
- Multi-standard digital video decoder (MPEG-2, H.264, MPEG-4)
- Integrated DVB-T/DVB-C channel decoder
- Integrated CI+
- Integrated motion accurate picture processing (MAPP2)
- High definition ME/MC
- 2D LED backlight dimming option
- Embedded HDMI HDCP keys
- Extended color gamut and color booster
- Integrated USB2.0 host controller
- Improved MPEG artifact reduction
- Security for customers own code/settings (secure flash)


THE TECHNOLOGY CHOICE
NXP established a new standard in LCD TV picture with Motion Accurate Picture Processing (MAPP), addressing the high-end digital TV market. Early in 2008, the company defined a new platform taking the functionality of the TV543 system and combining it with MAPP technology embedded in standalone PNX51xx PQ co-processors to address the mid- to high-end digital TV Market. The heart of this new platform is the TV550 SoC.

For such a big and complex SoC, NXP was looking for the most cost effective solutions in terms of selecting the right technology node. All the previous high-end digital TV SoCs were at 90nm. The functionality which was targeted to be implemented in PNX85500 would have required more than double the die size in 90nm and it was commercially not viable. For higher integration, NXP evaluated other advanced nodes.

45nm was chosen to be the most preferred node based on the cost and performance analysis. It would give the level of integration that was desired for the TV550 IC and it could also meet the required performance levels. At the same time, moving to 45nm created a challenge for our team as it relied on the latest TSMC technology. After a careful analysis of the TSMC process parameters, NXP decided to select 45nm, which effectively makes the PNX85500 the first ever TV SoC in the consumer electronics domain to be manufactured at 45nm.

THE IMPLEMENTATION CHALLENGE
The TV550 SoC is a complex design which implemented all the latest features of a Full-HD digital TV. Its design included multiple DSP and processor cores in a single package using flip-chip technology.

Also, this was a truly global project, consisting of specialized teams of NXP staff located in several countries. A team of 24 physical design engineers was formed in NXP Bangalore, supported by three architects and experts from NXP’s UK operations. These teams delved into the various nuances of 45nm technology. Another team based in the Eindhoven, Holland, lab contributed the architecture and basic technology, while a development team in Hamburg, Germany, assisted with the IP. There were a few key execution and technology challenges that our people had to overcome to develop the TV550. These were:
- the enhancement of Cadence SoC Encounter based flow;
- the estimation of maximum standard cell density leading to routing feasibility;
- developing the flow for Lithography (including CMP) checks and fixes;
- the run time analysis to estimate the compute server requirement; and
- RDL routing and bump placement for flip-chip design

The key design parameters were the five major frequency domains: 533MHz, 525MHz, 450MHz, 350MHz, 300MHz. Also, the main interfaces include LVDS, DDR Phy, HDMI, Ethernet, USB, Flash, SPI, PCI and I2C.

PNX85500 TOP LEVEL LAYOUT
Following the abutted design methodology, the team developed a netlist restructuring flow in which the 9T and 12T cells in the design was segregated to have only 12T cells partitioned into a block and the 9T cells in the other.

The reduced channel width of the 45nm transistor brought in new dimensions of engineering challenges such as the output drive impedance of the cell being much smaller than the trace impedance, leading to a change from a voltage source model (Nonlinear Delay Model or NLDM) to a current source model (CSM) for timing closure. The design also brought in roughly 200,000 hold violations, which the team had to fix in innovative ways. The team took the challenge of delivering this first 45nm design – effectively surmounting issues in the areas of layout and timing closure, resulting in a successful tape-out.

Author information
Neeraj Paliwal is the Country Manager for NXP India, and VP and SoC Factory Global Manager for NXP Semiconductors.