Bookmark and Share Printer-friendly version Email to a Friend

LDPC technology comes to disk-read channels

( 01 Oct 2009 )
By Ron Wilson, Executive Editor, EDN

LSI recently launched a new era in disk-read-channel technology with the RC9500, a mixed-signal read-channel-IP (intellectual-property)-core cluster. LSI intends the block for integration with a drive vendor’s IP to create a single-chip drive-electronics subsystem. The IP is LSI’s—and, possibly, the industry’s—first venture into 40-nm process technology, and it appears to be the first application of an LDPC (low-density-parity-check) algorithm in read-channel products. LSI intends the IP for the coming generation of 500-Gbyte/disk, 2.5-in. and 1-Tbyte/disk, 3.5-in. drives.

The 40-nm part allows the read channel to reach 4 Gbps within the power budget customers specify. At this speed, even minimal parasitics and small variations can sneak up on designers. Compounding the design problem for analog designers is the fact that the whole game in read channels is about noise. The head and media designers will push areal density until every hint of noise margin is gone, so there’s nothing left over for the low-noise-amplifier designers. But low-noise design at 40nm—especially in IP, in which you can’t control the charge other circuits might be pumping into the substrate next door—is an art. It would be easy for circuit designers to lose the whole advantage of the new LDPC algorithm in the analog section.

The 40-nm process also presents issues to LSI’s customers. LSI’s interface to customers using this IP will be its familiar ASIC model. But everything will go better if customers bring to the table a design team and IP that are ready for the rigors of a 40-nm design. The other milestone is LDPC, a signal-recovery technique that has for years found use in such areas as satellite communications, in which SNRs (signal-to-noise ratios) are small and no one minds that the receiver fills a rack and runs slower than real time. Getting the algorithm into a manageable gate count and power consumption and getting it to keep up with a 64-Gbps bit stream are challenges. But LSI officials claim that LDPC provides at least 1 dB of improvement in SNR—a major increment in disk drives.

The algorithm required some new architectural thinking compared with previous read-channel DSP designs. LSI designers also worked on adapting the algorithm to the signal characteristics they expected from the next generation of head and media designs, which are themselves still evolving.

LSI Corp.

 
Printer-friendly version Email to a Friend
Article Rating 
Average Rate: No rating yet
 
Poor Quite Good Good Very Good Excellent
 
 
Related Content 
 
 
ADVERTISEMENT
 
 
ON-DEMAND WEBCASTS

 
Highest Rated  
 
 
 
 
ADVERTISEMENT
 
 


TECHNOLOGY NEWS
 
 
 
PRODUCT NEWS
 
FEATURED SPONSORS
 
 
 
DESIGN CENTERS
 
ADVERTISEMENT
 
     
CURRENT ISSUE
 
COVER STORY:

Analog design in the 21st century: challenges, tools, and IC advances

We are now more than a decade into the 21st century, and on an ever-accelerating fast track to technological innovation in electronics. The transistor and progression into the IC, or microchip, lit the fuse leading to the explosion of innovations in electronics that is now taking place. Since the wi ...
HIGHLIGHTS:
SPECIAL REPORT
DESIGN FEATURES
 
PULSE
 
 
 
 


 


RSS
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   
   

POLL
What type of environmental regulation do you think will be most beneficial for the tech industry?
Proper recycling and disposal
Push for power efficiency and energy conservation
Chemical/lead regulation
View results

 
 
 
 
 
 
Power Technology E-newsletter 
Power.org Releases Power Architecture 32-bit Application Binary Interface Supplement
EDNA, May 11
POL Regulators Designed for Energy-efficient Computing
EDNA, March 11
Fairchild Revolutionizes Power Savings
EDNA, January 11
Lattice Transforms Board Power and Digital Management
EDNA, November 10
 
Analog E-newsletter 
12V Dual-channel Synchronous Buck Converter Features Integrated FETs
EDNA, February 10
Power MOSFETs features reduced top-side thermal impedanc
EDNA, January 10
 

 
KNOWLEDGE CENTER
 
Texas Instruments: DaVinci™ Technology
 
Texas Instruments: Safe Bet Series
 
 
INDUSTRY LINKS
 
Photonics Association (Singapore)
Singapore Industrial Automation Association (SIAA)
Taiwan Semiconductor Industry Association (TSIA)
 
 
 
 
OUR SPONSORS
 







Keithley Instruments
With more than 60 years of measurement expertise, Keithley Instruments has become a world leader in advanced electrical test instruments and systems from DC to RF (radio frequency). Our products solve emerging measurement needs in production testing, process monitoring, product development, and research...
 
 
 
     
 

EDN India | EDN Taiwan | EDN Korea | EDN Japan | EDN China | EDN | EDN Europe

 
ABOUT EDN Asia | | CONTACT US
   
© 2012 EDN Asia All rights reserved.