Synopsys Inc. has launched its Synphony HLS (High Level Synthesis) solution that integrates M-language and model-based synthesis to deliver up to 10X higher design and verification productivity than traditional RTL flows for communications and multimedia applications. Synphony HLS creates optimized RTL for ASIC and FPGA implementation, architecture exploration and rapid prototyping. In addition, Synphony HLS complements C/C++-based flows by generating C-models for system validation and early software development in virtual platforms. Synphony HLS integrates with Synopsys' Design Compiler, Synplify Premier, Confirma, VCS, System Studio and Innovator products to deliver the most comprehensive prototyping, implementation and verification flows from algorithm to silicon.
The Synphony HLS solution delivers significantly higher productivity than traditional methods by providing benefits such as:
• An automated flow from M to optimized RTL
• Synthesis of optimized RTL architectures for ASIC and FPGA
• Rapid prototyping methodology for early algorithm validation
• C-model generation for early software development and fast system validation
• Unified verification across multiple flows including prototyping and ASIC implementation
The Mathworks' MATLAB environment has been broadly adopted for algorithm exploration and design because it allows concise expression of behavior at an extremely high level of abstraction. The M-language models developed in this environment are typically re-coded and re-verified at the RT Level (RTL) and in some cases in C/C++ for implementation and verification. Unlike inefficient and error-prone manual re-coding flows, Synphony HLS creates implementable RTL and C-models directly from high-level M-language code and the Synphony HLS-optimized IP model libraries. Using a unique constraint-driven fixed-point propagation feature, designers can quickly and intuitively derive fixed-point models from a synthesizable subset of high-level, floating-point M-code. The Synphony HLS engine will then synthesize architecturally optimized RTL to meet area, speed and power goals. Synphony HLS allows designers to stay in their preferred algorithm modeling language, eliminating the need to re-code and re-verify models and enabling early system-level validation and verification.
Synopsys Synphony HLS
Synopsys
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