Semiconductor Manufacturing International Corp. (SMIC) has adopted Cadence Design Systems Inc.'s Litho Physical Analyzer and Cadence Litho Electrical Analyzer to more accurately predict the impact of stress and lithographic variability on the performance of 65nm and 45nm semiconductor designs. SMIC combined Cadence Litho Electrical Analyzer -- the semiconductor industry's first electrical DFM solution in production at leading semiconductor companies using process nodes from 90nm to 40nm -- with Cadence Physical Analyzer to create a flow that accurately predicted final silicon results.
Previously, the electrical behavior of individual cells and libraries could be pre-characterized in a single context that could be consistently applied to a given design based on the targeted process technology. At 65nm and below, each placement of a cell creates its own set of physical and electrical variabilities relative to its neighboring cells or surroundings. This "context dependent variability" is emerging as a critical issue that can cause the chip to fail. Cadence Encounter Digital Implementation System (EDI) System seamlessly integrates both the Litho Physical Analyzer and Litho Electrical Analyzer for rigorous context-dependent physical and electrical signoff of cells prior to full-chip implementation. The flow leverages model-based physical and electrical design for manufacturing (DFM) technologies to improve the quality and reliability of standard cell libraries and intellectual property (IP) cores, to increase manufacturing yield in full chips.
"The necessity to address physical and electrical variation at 65nm and 45nm requires a holistic approach that starts at the cell level and considers the entire context of the design," said Max Liu, VP of SMIC Design Services Center. "With the Cadence DFM flow, we could analyze cell and IP variability and accurately model their performance in real silicon. The solution also enables near-linear scalability, which is necessary for a full-chip electrical DFM verification flow."
Cadence has developed one of the industry's most complete design-side DFM prevention, analysis, and signoff methodologies, including design-side optimizations with Encounter Digital Implementation System. It is also being used for variability modeling of 32nm and 28nm libraries. "Fast, accurate context-dependent variability modeling of cells for both lithography and stress effects is key to implementing production-worthy designs at 65nm and below," said Dr. Chi-Ping Hsu, Senior Vice President of Research and Development for the Implementation Group at Cadence. "Numerous first silicon successes have already proven the value of DFM analysis tools for high-volume semiconductor designs."
Cadence
SMIC
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