The responsibility for yield at advanced process nodes has been steadily shifting from foundries toward chip design teams. The reason traces back to an equally gradual shift in failure mechanisms from random defects—caused by particle contamination and solely the responsibility of the fab—to a panoply of design-dependent failure modes. These modes include patterns that the litho, etch, and CMP steps corrupt; layouts or circuits that are too sensitive to process variations; and other interactions between the design and the process. Responsibility for these so-called systematic failures has to be shared among process developers, design-rule writers, and physical design teams. According to data from a 2006 ISSM paper by PDF Solutions, by 65nm these systematic defects caused the majority of die failures.
But involving design teams in the yield-learning process presents a problem. There has been no efficient way of linking process metrology or wafer-test data back to the design database so it could mean something to chip designers. Synopsys attacked this problem in March with the announcement of Yield Explorer—an attempt to fuse fab and test data with the design data and subject the resulting database to heavy-duty statistical analysis.
Today Mentor Graphics has taken a step in the same direction, but with significant differences. The company announced a new brand—Tessent—under which it will integrate its diverse portfolio of test and yield-analysis products and connect them into a single platform. The products will include Mentor's own test pattern generation (ATPG) and test vector compression tools, tools acquired with Mentor's acquisition of NXP's test group in May of last year, logic and memory built-in self test (BIST) tools acquired with the purchase of LogicVision in August of this year, LogicVision's unique PLL and SerDes BIST technology, and a new set of failure diagnosis and statistical analysis tools.
Beyond the Tessent brand, today's announcement also unveiled the latter-mentioned two new products: Tessent Diagnosis and Tessent YieldInsight. Diagnosis is a data-correlating tool that fuses test data from both BIST and ATE sources with the design database so designers can view fault data on routing or die maps. By comparing suspected-failure data against the actual chip layout, Diagnosis also provides fault-isolation tools that pare down the possible physical locations of a suspected fault to speed failure analysis. For instance, the tool can narrow down possible locations for a bridge fault to places on the die where the shorted nets actually lie adjacent to each other.
YieldInsight, in contrast, is a statistical package. According to Mentor vice president and general manager for Design-to-Silicon Joe Sawicki, YieldInsight offers automated analysis and presentation routines for Pareto, zonal, and wafer-map plots, among others.
As in other approaches to applying manufacturing test data to yield analysis, Tessent will require some changes in thinking on the test floor. Normally, test designers code tests to halt at the first failure on a die in order to sort failed from good dice as quickly as possible. But in order to collect the data necessary for yield analysis, test routines will have to continue running beyond the first failure to gather more data on each die. This will both complicate test programming and extend time on the test head during the yield-ramp phase of a chip's product life. But the increase in the rate of yield learning should more than compensate for these added costs.
Part of the longer-term promise of products such as Tessent is the ability to use feedback from test data not only to diagnose failure modes but also to adjust test strategies. In principle, rapid diagnosis can both direct test developers to check for the most likely failures earlier in the test program and direct design-for-test engineers to instrument designs for diagnosis of particularly troublesome failures. Both of these should be additional helps in achieving yield goals on schedule.
But the greatest promise of the combined product group may lie in the least-discussed corner of the announcement. The PLL and SerDes BIST products from LogicVision were the tip of a very important iceberg: a long-term effort to develop a systematic BIST approach for all analog circuits. This work is continuing with added resources and emphasis inside Mentor, Sawicki suggested. An effective analog self-test strategy coupled into a design-aware yield-learning system could help avoid the major train wreck that many designers see coming as analog circuits push deeper into the complexities of advanced process nodes.
Mentor Graphics
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