Walden C. Rhines, CEO and Chairman of Mentor Graphics Corp., one of the leading electronic design automation (EDA) companies worldwide, recently delivered a keynote at the EDA Tech Forum 2009 in Noida, India. In an interview with
EDN Asia, Rhines talked about some of the challenges designers are facing amid the growing SoC complexities, as well as shared his views on Asia and India as a market and as a design and development center. Excerpts:
EDN Asia: What are the benefits the designer should expect with Mentor Graphics acquiring LogicVision?
Rhines: LogicVision is a leader in Built-in-Self-Test (BIST) technologies. Mentor is a leader in embedded test pattern compression technology and Automated Test Pattern Generation (ATPG). Designers are facing new challenges as they move into lower nodes. The combination of Mentor and LogicVision will enable them address all aspects of full-chip test requirements with a unified test platform. The integrated solutions that we can now offer address the growing complexity of silicon test.
EDN Asia: Do you see any more consolidation in the EDA industry? Is there any renewed attempt at Cadence-Mentor Graphics merger?Rhines: I am not aware of any such attempt. Consolidation is a regular feature in the EDA industry, with 15 or more acquisitions per year on an average. But the basic structure of the industry—with the top three companies overwhelmingly dominating the whole EDA industry—has remained the same over the last several years, and there does not seem to be any change in this structure.
EDN Asia: What are the top three problems for the designer with growing SoC complexities, and how is Mentor addressing these?Rhines: The top three problems are design for low power, growing complexity of functional verification, and challenges of manufacturing variability whose percentage is becoming larger. Low power is an important differentiator in designs. Mentor has complete design flow for low power, starting at system level and going all the way to detailed physical layout. No other EDA company has this ability. Mentor’s Vista platform enables users to model, analyze, and optimize power at the transaction level of abstraction. Together with other Mentor products, Vista provides an end-to-end solution for low power design, verification, and implementation. Mentor has expanded its Reference Flow offerings to cover the total IC design cycle from systems level through functional verification, physical verification, and silicon test, while offering new solutions for low power, manufacturing variability, and silicon yield analysis. Within the Olympus-SoC and Calibre platforms DFM capabilities have been expanded and more tightly integrated to address manufacturing variability issues at nodes as low as 28nm and below. Mentor provides implementation solutions in TSMC Reference Flow, with advanced features such as on-chip variation and low-power design.
EDN Asia: How does Mentor Graphics look at Asia and India both as a market and as a design & development center?Rhines: Asia is the fastest growing region in the world for Mentor, and also for EDA. The company has extensive design & developmental work going on in Asia, and we shall continue to take advantage of the high skills at comparatively low cost available in this region. Mentor Hyderabad is our corporate R&D center, focusing on R&D in PCB systems, Hardware/Software Co-Verification, DFT, Physical Design and Verification, and other areas. Mentor Noida is another corporate R&D center. This center is doing R&D in Scalable Functional Verification, FPGA synthesis, Debug Tools with advanced GUI, and HDL compilers for various EDA tools. Asia has acquired the capability of doing designs at the latest nodes, and design tools are being made in Asia to cater to the local design needs.
