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Statistical analysis of test failure data improves IC yield

( 01 Jan 2010 )
By Stephen Las Marias, Editor, EDN Asia

ICs currently being developed at 65nm nodes and below exhibit an increased sensitivity to small manufacturing variations. As such, new design-specific and feature-sensitive failure mechanisms are on the rise. However, complex interactions between the manufacturing process and inherently more sensitive layout features are causing systematic yield-related issues. In effect, IC manufacturers need a yield analysis methodology capable of employing logical design and layout information along with high-volume test failure data.

In an answer to that, Mentor Graphics Corp.’s has released the Tessent YieldInsight yield analysis solution, which statistically analyzes large volumes of production test failure diagnosis data produced by the Mentor Graphics Tessent Diagnosis tool, helping manufacturers recognize, locate and fix design- and process-related yield problems to improve IC manufacturing quality levels.

The Mentor Graphics Tessent solution combines the automated scan test failure collection and diagnosis capabilities in the Tessent Diagnosis tool with advanced statistical analysis and data mining techniques in the new Tessent YieldInsight product. The Tessent YieldInsight tool brings innovative design-correlated analysis methods that supplement traditional fab-centric yield management systems.

In a manner consistent with yield and failure analysis tools, the Tessent YieldInsight steps the user through the process of selecting and filtering populations of failing die, grouping die that are failing for similar reasons, and analyzing various aspects of these populations to identify and locate systematic yield loss mechanisms.

“Mentor’s yield analysis solution will make a huge impact on our customers’ ability to rapidly ramp their production yield,” said Joseph Sawicki, Vice President and General Manager for the Design-to-Silicon Division at Mentor Graphics, in a statement. “For the first time in the industry we are really closing the design-to-silicon loop by extracting statistical information from silicon test failure data and using it to identify precisely where in the design or manufacturing process we can best impact yield and quality.”

Mentor Graphics Corp.
www.mentor.com

 
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