UMC and Xilinx Inc. have fully qualified the Virtex-6 FPGA family on the foundry's high- performance 40nm logic process. The qualification is the result of the close work between engineering teams from both companies to further enhance yield, reliability and cycle time. The full qualification of the Virtex-6 family signifies the transition to 40nm volume production following UMC's first shipments of the devices in March 2009.
"We highly value the ongoing execution of our long time manufacturing partner UMC," said Xilinx CEO Moshe Gavrielov. "We have collaborated together to deliver several generations of industry leading FPGA families."
"This 40nm achievement follows a long history of successful product family launches with Xilinx," said UMC CEO Dr. Shih-Wei Sun. "Today's production readiness of the 40nm Virtex-6 family underscores our ongoing commitment to Xilinx and our long-term partnership."
Built using third-generation Xilinx ASMBL architecture, the Virtex-6 FPGA family delivers 15 percent higher performance and 15 percent lower power consumption compared to competitive 40nm FPGA offerings. The devices operate on a 1V core voltage with an available 0.9V low-power option and are supported by a new generation of development tools delivered by ISE Design Suite 11 and a vast library of IP already available for the market leading 65nm Virtex-5 FPGA family to ensure productive development and design migration.
"Reaching the production milestone means we have stable and predictable yields that allow us to meet our growing customer demands reliably," said Vincent Tong, Xilinx Senior Vice President, New Product Introductions and Worldwide Quality. "This would not be possible without the joint collaboration with UMC where we used Xilinx's next generation FPGA diagnostic tools along with UMC's rapid info-turn yield learning vehicles to achieve significant yield and quality improvement of 40nm."
Early engagement, design for manufacturing and an effective test vehicle process are also contributing to the successful roll-out of the Virtex-6 family. By building on what they learned from working together closely on previous generations, the Xilinx and UMC engineering teams were able to beat the tape-out to production duration of the Virtex-5 family by a quarter, Tong noted.
"The successful qualification of Virtex-6 is the result of the close teamwork between Xilinx and UMC engineers to address the challenges of 40nm high performance technology," said S.C. Chien, Vice President of Advanced Technology Development at UMC. "UMC dedicated significant engineering talent and resources in our joint effort with Xilinx, such as customizing device specifications to their product specifications, delivering DFM for stable yield, fast info-turn vehicle to enhance quality, and quick diagnosis methodology. We are excited to see that our teamwork has paid off with today's milestone."
UMC's independently developed 45/40nm logic process utilizes sophisticated immersion lithography for its 12 critical layers and incorporates the latest technology advancements such as ultra-shallow junction, embedded silicon- germanium and mobility enhancement techniques, and ultra low-k dielectrics. Currently, several customers have 45/40nm products being manufactured at UMC, with thousands of wafers having already been shipped.
Virtex-6 FPGAs are the programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable designers to focus on innovation as soon as their development cycle begins. The Virtex-6 FPGA family comprises three domain-optimized FPGA platforms that deliver different feature mixes, including DSP slices, memory blocks and serial transceivers supporting up to 11.2Gbps to best address a variety of customer applications. Currently, six out of nine Virtex-6 family base devices are shipping. All nine are scheduled to be available in production volumes by the end of the second quarter of CY2010.
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