The race for being the first to reach lower nodes will see fewer players at 32nm and below. The design and manufacturing costs at these nodes are prohibitively large and unaffordable for most semicon vendors. Intel and TSMC are among the few companies investing into manufacturing at these nodes. Intel has announced an investment of $7 billion in 2009-10 for upgrading plants to support 32nm process technologies. Intel’s Westmere is the Nehalem architecture migrated from 45nm to 32nm.
Fabless modelMost semicon makers are going for the fabless model, already opted by TI, Sony, STMicroelectronics, and Fujitsu. Companies are also forming alliances to decrease their costs, such as that between Matsushita and Renesas and between ARM and Global Foundries. The Common Platform Technology Alliance, comprising IBM, Chartered, and Samsung, is the biggest of such alliances. A major step was taken toward 32nm designs when this alliance qualified Synopsys IC Validator for 32nm process design rule checking on Common Platform technology. Synopsys and the Common Platform allies are going ahead with the collaboration to complete the qualification of IC validator at 28nm on Common Platform technology.
Important differences have emerged between 45nm and 32nm design and manufacturability. There is less relative copper loss and higher variability at 32nm than at 45nm. At the block level rather than at the circuit level the 32nm showed 55 percent reduction in area as expected, 40 percent drop in leakage, and a 30 percent reduction in dynamic power. ARM, which has significant experience at 32nm and below having implemented end-to-end design flows, is in continuous interaction with Common Platform to co-optimize processes and IP, and has reported a surprise result—a 24 percent increase in maximum clock frequency. Is this pay-off due to gate stack or due to advances in cell design and place/route technology? The answer is not clear.
In-design physical verification is emerging as a great challenge at 35nm. The prevalent approach to physical design and verification is best summed up in the expression “implement-then-verify.” This approach results in a lot of iterations between design and signoff, increasing costs, which become exorbitant at 32nm and lower nodes, thereby making in-design physical verification an important way to keep costs under control by reducing physical verification turnaround time. IC Validator, which is the latest addition to the Galaxy Implementation Platform and a full signoff DRC/LVS solution, is an add-on to IC compiler for in-design physical verification. It enables place and route engineers to accelerate time to tapeout and improve manufacturability by enabling physical verification within the implementation flow, thereby letting Common Platform customers deploy IC Validator into production at 32nm and reap the advantages of in-design physical verification in conjunction with the IC Compiler place and route solution.
HKMGThe most significant change at 32nm from the previous nodes is HKMG (High K Metal Gate). 32nm low power HKMG is available now in Beta PDK 7/31/2009. The technology is migratable to 28nm. These developments have provided some visibility into still lower nodes of 22/20nm and 15nm. The possibility of HKMG Tinv (thickness of the inversion layer under the gate) scaling at 22/20nm and 15nm is now more or less settled, as is computational lithography to extend immersion optical lithography.
The libraries at these nodes are not like those at the earlier nodes. ARM reports that the family of libraries needs to be branched out into far greater numbers. First, there are the Foundation libraries, which are general-purpose digital libraries. But at 32nm with the traditional cell-based flow breaking down, two more levels of library IP—Enhanced and Enhanced-Core—come into being. These include IP libraries developed for implementing specific ARM cores, such as libraries with power-gating optimizations for implementing CPU cores, ultra low power memory compilers, area-optimized libraries for graphics core, etc.
Another new feature is what ARM calls multi-channel library design. These provide pairs of footprint-compatible cells with two different channel lengths, without using any additional mask layer. From the designer viewpoint this means finer grained control over the leakage/speed tradeoff with no change in design flow.
