A highly integrated solution for AC adapters

In recent years, the demand for notebook PCs has continued to grow as many consumers opted to replace their desktop PCs. This growth is not only because of their compact size and light weight, but also because the reduced price of these electronics, which makes them more appealing to consumers. Subsequently, the trend in AC adapters is moving towards smaller size, higher efficiency, and lower price. This paper will explore a highly-integrated boundary-conduction mode (BCM) PFC and quasi-resonant (QR) PWM combo controller to address these challenges.

The increasing effort towards high power density and high efficiency QR converter lead us to develop converters capable of operating at higher switching frequency with high efficiency. For this reason, QR PWM converters have drawn lot of attention due to their high efficiency, high switching frequency, and high power density. Figure1 shows the system architecture of a QR PWM converter. This low cost and high efficiency solution combines boost converter PFC stage and single flyback PWM stage. Both of the two stages are properly controlled by the single combo controller.

The power supply operates from a universal input and is designed to provide a single output delivering 75W~150W continuous. Additionally the power supply offers various protection features, including:
- RT-OTP, DET-OVP, VDD-OVP with latching shutdown and fast AC reset
- Auto-restart overload protection with fast AC reset
- Primary sensed output overload protection

Operation principle of PFC stage
The turn-on sequence of the PFC MOSFET is determined by the zero current detection since the PFC stage operates at boundary conduction mode. As shown in Figure 1, the mechanism can be achieved by detecting the information on an auxiliary winding of the PFC inductor. Once the detected voltage signal is lower than the triggering voltage, the PFC gate will be turned on to initiate a new switching cycle.


FIGURE 1

As for the turn-off sequence, the traditional way is fixed on time control. In steady state, considering one switching cycle, the input voltage vg can be viewed as a constant voltage. According to Figure 2, when the MOSFET Qb is switching, the inductor current ramps up and down linearly, and the peak value can be expressed as




FIGURE 2

Since the feedback signal of PFC output voltage in steady state is almost constant during one half AC cycle, with a fixed frequency saw-tooth generator, the fixed on-time control can be achieved. Therefore, iLpeak will automatically follow the input voltage Vg to perform a natural power factor correction mechanism. Figure 3 shows the typical inductor waveform in one half AC cycle.


FIGURE 3

By the average area of the triangular waveform of the inductor current, the average current iLavg can be derived from Eq. (1) and expressed as



However, the problem of the fixed on time control is that the bandwidth of the error amplifier is so narrow that it has poor transient response. In order to improve this weakness, the patent innovated multi-vector error amplifier (US Patent 6,900,623) has built in a transconductance type controller. As shown in Figure 4, the PFC output voltage is detected by an external voltage divider that consists of R1 and R2. When PFC output variation voltage reaches more than 6 percent or less than 8 percent of the reference voltage Vref, the multi-vector error amplifier will adjust its output sink or source current to increase the loop response to simplify the compensated circuit.


FIGURE 4

As shown in Figure 5, the output of the error amplifier is compared with the internally generated saw-tooth waveform to determine the on-time of PFC gate. Normally, with lower feedback loop bandwidth, the variation of the PFC gate on-time should be very small and almost constant within one input AC cycle. However, power factor correction circuit operating at light load condition has a usual defect, the zero crossing distortion, which distorts input current and makes the system’s THD (Total Harmonic Distortion) worse.


FIGURE 5

In order to improve THD at light load condition, especially at high input voltage, an innovated THD optimizer (US Patent 7,116,090) is built-in. The optimizer samples the voltage across the current sense resistor, and the sampled voltage is added to the saw-tooth waveform, as shown in Figure 5, to modulate the on-time of the next switching cycle. As a result, the compensated PFC on-time around the valley of AC input voltage will be wider then the original, while the PFC on-time around the peak voltage will be narrower. The timing sequences of the PFC MOS and the shape of the inductor current are shown in Figure 6.


FIGURE 6

Also, Figure 7 shows the difference between calculated fixed on-time mechanism with and without THD Optimizer during a half AC cycle.


FIGURE 7

Protection functions of PFC stage
With AC voltage detection property, the controller can perform Brown-in/out protection (AC voltage under voltage protection). The AC input voltage is detected through a resistor divider and an RC filter (Figure 1) such that the filtered signal is proportional to the AC voltage level. When the AC voltage drops after a period of debounce time, the under voltage protection will be activated and the output of the multi-vector error amplifier, Vcomp will be clamped at a low level. Because the duty of PFC switching is determined by comparing the saw-tooth waveform and Vcomp, as shown in Figure 5, lower Vcomp results in smaller PFC on-time, and therefore the energy converged will be limited and the PFC output voltage will be decreased. When the feedback PFC output voltage, Vinv is lower than a threshold voltage, the controller will stop all PFC and PWM switching operation immediately until VDD (power supply of the IC) drops to turn-off voltage then raises to turn-on voltage again (under voltage lock out, UVLO). Once the AC input voltage is back to a regular level, and VDD reaches turn-on voltage again, then all the switching operations will be back to normal operation.

There are still many protections of PFC stage, such as PFC output over voltage and under voltage protection and over current protection. These protections are very basic and straight forward, and will not be introduced in this article.

Operation principle of PWM stage
The PWM turn-on sequence is determined by the valley detection. During the off-time of PWM switch, when transformer inductor current discharges to zero, the transformer inductor and the parasitic capacitor of PWM switch will start to resonate. When the drain voltage of PWM switch falls, the voltage across on auxiliary winding vaux will also decrease proportionally since auxiliary winding is coupled from primary winding. Once Vaux resonates and falls to negative, the controller will internally clamp VDET at a low level, Vclamp and flow out a current, iDET. The magnitude of iDET is proportional to the amplitude of Vaux. The valley detector will compare this iDET with a threshold level, and if iDET rises over this level, PWM gate will be triggered.


FIGURE 8

The PWM turn-off sequence is determined by the output feedback voltage, VFB and PWM MOSFET sensing current. The feedback voltage is proportional to the output loading. Once the sensed current signal reaches VFB, then the PWM MOSFET will be turned off.

As mentioned, PWM will initiate a new switching cycle once the first valley signal is detected. However, when the output load is decreased, the energy stored in the transformer is also decreased, so that the magnetizing inductor discharge time is reduced, which leads to extremely high switching frequency at light load. In order to solve this problem, the off-time modulation technique is introduced to regulate switching frequency according to VFB. When output loading is decreased VFB becomes lower, and internally the PWM minimum off time, tOFF-MIN, will be extended according to Figure 9.


FIGURE 9

This tOFF-MIN can be viewed as a period of time that blanks the valley signal. After tOFF-MIN, once the valley signal on the auxiliary winding is detected, then the PWM gate signal will be sent out to initiate a new switching cycle.

With the frequency-regulation curve, at light load condition, the power system can perform extended valley switching and reduce switching loss. According to Figure 9, when VFB is lower than VG, tOFF-MIN is extended to tb, so that PWM stage enters burst mode operation to further reduce the switching frequency and get better conversion efficiency.

Generally, when the power switch turns off, there is a delay time from gate signal falling edge to power switch off. This delay time is produced by internal propagation delay of the controller and turn-off delay time due to the gate resistor and gate-to-source capacitor Ciss of the PWM switch. Under different AC input voltage, this delay time causes different maximum output power under the same PWM current limit level. Higher input voltage leads to higher maximum output power limit since the rising slope of the magnetizing inductor current is higher. It results in higher peak inductor current during the same delay time. Therefore, in order to make the maximum output power limit at the same level under different input voltage, the controller needs to regulate the maximum limit voltage of PWM current sense, VCS-limit to limit PWM switching current.

Referring to Figure 1, when PWM MOSFET Qf is on, the auxiliary winding voltage, Vaux, carries the information of input voltage, Vin, which can be expressed as



where Na and Np are the turn number of auxiliary and primary winding respectively. So as Vin increases, the magnitude of Vaux becomes higher as well. As mentioned, the controller flows out a current, iDET when Vaux is negative, and iDET can be expressed as



where RDET is the resistor connected between auxiliary winding and the controller as Figure 8 is shown. Since the current iDET is in accordance with Vaux, which carries the information of input voltage, the controller can depend on iDET to regulate VCS-limit to perform over-power compensation at different line voltage. The characteristic curve of iDET versus VCS-limit is shown in Figure 10. As the input voltage increases, Vaux become higher as well as the current iDET, and the controller regulate VCS-limit to a lower level to provide compensation.


FIGURE 10

In addition to valley detection and over power compensation, vDET also carries the information of output voltage when Qf is off, so that the output over voltage protection can be achieved. As Figure 11 is shown, during the discharge time of PWM transformer inductor, the voltage across on auxiliary winding is reflected from the secondary winding.


FIGURE 11

Therefore, the flat voltage of vDET is proportional to the output voltage and can be expressed as



where Ns is the turn number of the secondary winding, and RDET and RA are the resistor connected between auxiliary winding to the controller as Figure 8 is shown. So the controller can sample this voltage level to perform output over voltage protection. The sampled flat voltage level is internally compared with a threshold voltage, once VDET exceeds this threshold voltage for a period of debounce time, the protection is activated and the IC will enter latch mode. By doing so, the controller can protect rapidly by this kind of cycle-by-cycle sampling method in case of output over voltage. The protection voltage level can be determined by the ratio of external resistor divider RA and RDET.

There are still many protections of this controller, such as VDD over voltage protection, adjustable over temperature protection, output open loop, short circuit, and over load protection. These protections are also very basic and will not be introduced in this article.

Conclusion
This paper has presented a new combo solution (BCM PFC+QR PWM) with a simple and compact configuration. This converter can achieve high efficiency at high input voltage. Besides very low switching loss, the power saving of this converter is lower than a traditional PFC+PWM converter because of the two level PFC and deep extended valley detection. When looking at the efficiency, the rectifier shows that this converter can get 1.5 percent to 2 percent improvement on the efficiency.

Author Information
Jhih-Da Hsu and Chi-Sheng Chao are product engineers at Fairchild Semiconductor.


Caption
Fig. 1: Application circuit diagram.
Fig. 2: Typical switching waveform of PFC stage.
Fig. 3: Controlled on-time inductor current waveform.
Fig. 4: Block diagram of the multi-vector error amplifier.
Fig. 5: PFC current loop and voltage loop controller block diagram.
Fig. 6: Fixed on-time control with and without THD optimizer comparison diagram.
Fig. 7: Calculation result comparison of the average input current.
Fig. 8: Block diagram of PWM valley detector.
Fig. 9: VFB versus tOFF-MIN frequency-regulation curve.
Fig. 10: iDET versus VCS-LIMIT curve.
Fig. 11: Typical Waveform of vDET.