Xilinx Inc. will demonstrate the latest breakthrough 40Gb Optical Transport Network (OTN) developments for integrated multiplexer/transponder (muxponder) applications at the 2010 Optical Fiber Communication Conference and Exposition. The demonstration combines proven partial reconfiguration technology from Xilinx with OTN IP solutions from Avalon Microelectronics Inc. to significantly reduce downtime and lower the bill of materials (BOM) cost and power consumption of multi-port (channel) networks.
Network operators can reduce overall capital expenditures (CapEx) and operating expenses (OpEx) with 'on-the-fly' reconfiguration of a selected port or multiple ports without having to power down the entire line card and when other ports are still up and running. Using the unique partial reconfiguration capabilities available with Xilinx's high-performance Virtex FPGAs, developers can also reduce muxponder size by 30 to 40 percent and lower power consumption as compared to devices without partial reconfiguration.
Partial reconfiguration is the ability to dynamically modify logic blocks by downloading partial bit files without interrupting the operation of the remaining logic. The 40G OTN muxponder demonstration system deploys this technique to enable four independent ports (client channels) with support for OTU2, OC-192/STM-64, and 10GE LAN industry standards as examples. It uses an Avalon 40G test board (Anaconda) jointly developed with Xilinx using two Virtex-5 LX330T FPGAs. An external 10G tester is connected to generate traffic and monitor each port for interference.
Each channel can be reconfigured on the fly by re-loading a partial bit stream to the Xilinx FPGA that instantiates only the chosen port persona rather than all possible port configurations as required by ASSP and ASIC implementations. This approach enables developers to use fewer and smaller devices to implement the FPGA-based 40G OTN muxponder. Developers can also save 30 to 45 percent of the logic capacity available in the two Virtex-5 devices and lower power consumption by eliminating the need to instantiate multiple clients per channel. For applications targeting the latest generation Virtex-6 FPGAs, single-chip implementation may be possible depending upon the specific configuration.
Demonstrations by Xilinx and Avalon can be seen at OFC 2010 from March 23rd through March 25th at the San Diego Convention Center.
Xilinx
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