DRAM giant Hynix and IP vendor Innovative Silicon have announced work that offers an alternative future for the DRAM industry beyond the 30nm half-pitch. Using 3D transistors similar to FinFETs, the two companies have demonstrated behavior similar to the floating-body effect in SoI planar transistors. IS claims the effect is strong enough and has the right characteristics to implement a capacitorless, one-transistor DRAM that can meet DDR3 voltage, power, and performance specs at and beyond the 50nm half-pitch. By 30nm, according to IS senior vice president of marketing and business development Jeff Lewis, the floating-body memory will have a significant cost advantage over conventional stacked-capacitor DRAM as well.
Today's floating-body memory, which IS calls Z-RAM, depends upon a retained charge in the electrically isolated region between the channel and the insulating substrate of a planar SoI transistor. When the transistor conducts in a high-voltage mode, charge accumulates in this region, altering the transistor's threshold voltage. Since there is no path for the charge to escape, the threshold voltage remains altered until the charge is removed by a resetting current. A small read voltage can sense the state of the threshold. Thus a single transistor serves as a bit cell, with one pair of voltages for set/reset and a lower voltage for sensing.
Z-RAM has attracted a good deal of attention, not least from Hynix, which has licensed the technology. Other companies have been researching floating-body memory as well, but with less public comment. But several issues have dogged the technology. One has simply been that Z-RAM requires SoI wafers, whose initial cost is higher than the cost of bulk wafers. That difference is an issue in the DRAM market, with its huge volumes and tiny margins. Another cost-related issue is that Z-RAM uses a relatively high voltage for writing, necessitating on-chip charge pumps and increased power consumption.
The third issue is more technical. The planar SoI cell is subject to gradual disturbance from activity in nearby cells, limiting the time the cell can retain data between refreshes—the so-called dynamic retention time. This is a slightly different issue than the (usually much longer) static retention time, which is the time required for an undisturbed cell to leak itself into an uniterpretable state.
The new cell design addresses all these issues. Totally unlike the planar Z-RAM cell, the new device uses a unique vertical transistor that looks somewhat like a FinFET with a cap on it. The transistor Source is an N+ region sitting on top of the bulk silicon. The body of the transistor is a fin, apparently of undoped or lightly-doped poly, standing vertically above the source, and a cap of N+ material on top of the fin forms the Drain. The sides of the fin are clad in gate dielectric, and then the fin is sandwiched between two gate electrodes, forming a dual-gate vertical FinFET.
The current path, Lewis says, is vertical, between the two N+ regions. Lewis did not go into further detail about the operation of the device, but it appears the transistor reads in partial-depletion mode, with channels forming just at the dielectric interface on either side of the fin. This would allow charge to accumulate and become trapped by the low mobility of the lightly-doped material in the undepleted center of the fin, where it would act as a floating body to alter the device's threshold voltage. Presumably a relatively small increase in gate voltage during conduction would be sufficient to extend the depletion regions and sweep away the trapped charge. But this is speculation.
Lewis explained that since the bottom N+ region formed an isolating junction with the intrinsic bulk silicon beneath it, there was no need to fabricate the transistor on an insulating layer, and hence the process could use bulk silicon wafers. In fact he suggested the process of forming the transistor was not unlike that already used for recessed-channel array transistors (RCATs) in today's DRAMs. For reasons IS is withholding until Hynix presents a paper at the VLSI Symposium, the device reads and writes at under 1V, keeping both the operating voltage and the projected array power consumption with the DDR3 roadmap limits. Lewis said the performance would also meet DDR3 requirements, citing estimated 5-7ns read and write times in a 50nm process.
Innovative Silicon
Hynix
