Purveyors of modern, high speed logic would like to think of their products as the center of the technological universe, and perhaps they are right. But before information gets to the center, it needs to travel from its peripheral origins, and, to be useful, the processed information needs to travel back out to the periphery— that cluttered nonsilicon world of people, machines, and their natural surroundings. And, despite the fondest wishes of those whose world extends nary a micron beyond the core, the natural universe—far away from convenient, familiar, and occasionally self-serving abstractions—remains steadfastly analog.
There is no doubt that analog IC technologies have followed logic down the path to smaller signal swings, greater integration, and the enormous economies of scale associated with vanilla CMOS and its near variants. Indeed, by taking advantage of fab equipment just a few process generations older than the current state of the art, analog and mixed-signal-IC manufacturers have benefited from high-yielding, low-voltage processes running on largely depreciated equipment, further reducing factory costs.
Accordingly, analog-signal processing blocks operating on fewer than a handful of volts have enjoyed great commercial success and garnered impressive profits for those companies that can ply the analog craft within the confines of CMOS-IC technologies.
As economic as low-voltage signal processing is, such technology is rarely suitable for an application’s physical interface, which defines the electrical conditions for analog-I/O structures.
Thus, though industrial applications typify the requirements and design challenges related to robust interface-circuit design, similar issues arise in environments as disparate as test-and-measurement instrumentation, medical electronics, automotive systems, communications, and consumer electronics. Yet, until fairly recently, most of these applications depended on semiconductor-fabrication processes that have evolved over the years but rarely enjoyed a significant departure from their evolutionary track. Meanwhile, the economic forces that drive low-voltage-IC designers toward smaller geometries can work against chip makers that must accommodate large signal swings (see box “The economies of scaling”). Recently, several major analog- and mixed-signalsemiconductor manufacturers have deviated from this trend, developing new, more compact processes and still preserving the robustness that I/O functions require.
Little processes that can
The dielectric breakdown of device layers, such as gate oxides, often limits the operating voltage for a given process and device design.
But that view looks from the process outward with operating voltage as a parameter—a reasonable perspective as long as a sufficient SNR is attainable within the signal voltage limits that the process imposes. Indeed, considering the energy required to charge stray capacitances with every signal transition—EC=C(∆V)2/2—small operating voltages bring a disproportionate energy savings.
But the view from an industrial application’s perspective differs greatly. In this case, nominal signal voltages are given—commonly ±5 or ±10V—and other attributes in the IC manufacturer’s domain are parametric. The problem isn’t to scale signals to the device capability, but to scale the device capability to the signal requirements. This distinction affects more than just minimum dimensions, such as gateoxide thicknesses and electrical lengths; minimum-sized devices do not dominate designs in these applications to the extent that they do in, say, logic designs.
Furthermore, the larger operating voltages not only affect individual devices, but also increase device spacing to isolate adjacent devices.
An increase in the spacing between devices results in a total area devoted to an individual device that grows a bit faster than linearly (Figure 1).
Process and device engineers— in many ways the unsung heroes of the semiconductor industry—have for decades been striving to make gains on the voltage/scale curve, using combinations of process chemistry and device physics.
Virtually all of the large analog- and mixed-signal-semiconductor suppliers have put significant effort into these developments. One new process that exemplifies the trend is iCMOS from Analog Devices, which the company announced at the most recent Electronica show in Munich. Comparisons between iCMOS and older high-voltage processes indicate the extent of the newer processes’ space savings (Figure 2). In addition to saving valuable chip real estate, the process also brings improved
power efficiency and provides the means of integrating signal conditioning and -processing circuits on the same chip.
“Industrial designers considering an analog-CMOS [signal-processing] product for its cost or power efficiency benefits were forced to add significant levels of signal conditioning [and] signal biasing ... to get the high speed and low power consumption required to interface [signal-processing functions] to high-voltage industrial systems ranging from actuators to sensors,” according to Denis Doyle, a process-development fellow at Analog. “Under those conditions, manufacturing technologies capable of handling 30V were in the range of 3 to 5 microns, and adding digital functionality caused [chips] to grow to unacceptable sizes.” By contrast, the new submicron process allows greater integration by isolating small lower voltage parts from the substrate potential, which provides chip designers greater freedom to move signals from the I/O level to lower voltages on one die (Figure 3).
The modular process includes two sets of complementary bipolar transistors. One set can operate to 16V and features cutoff frequencies of 6 and 4GHz for the npn and pnp, respectively. The second set can operate to 30V and yields a 1GHz cutoff frequency for both polarities. Additional process modules provide switchable polysilicon-polysilicon capacitor arrays and low-temperaturecoefficient and low-voltagecoefficient thin-film resistors, which provide good initial ratiometric matching and an in-factory trim capability. On-chip memory and logic capability allow both factory and OEM chip configuration.
As advanced high-voltage analog processes displace older processes less able to support high levels of integration, both IC and OEM designers will have reason and the rare opportunity to rethink long- established segmentation schemes for common I/O signal chains. In the meantime, the most immediate use of the technology is likely multichannel versions of individual functions and die and package reductions of single-channel devices.
In both cases, chip makers may be able to provide OEMs with significant savings, not only by shrinking the silicon area to implement a function, but also by bringing more of the off-chip components onto the die.
The six-channel AD7656 ADC is a good example of the trend. An input structure, including six on-chip track-and-hold amplifiers, accepts signals in either a ±5 or ±10V range, programmable in channel pairs. Each amplifier feeds a 16-bit SAR (successive-approximation-register) converter. Application circuits can simultaneously trigger the six converters or independently trigger converters in pairs. The sample rate is 250k samples/sec per channel, and the full-power bandwidth is typically 8MHz, allowing you to use the 7656 in undersampled applications.
Minimum SNR and maximum THD are 83dB and –97dB, respectively. The converter’s dc performance specifications include ±2.1mV zero error, ±4LSB maximum integral nonlinearity, and no missing codes to a 15-bit resolution. The converter’s output data is available through both parallel and highspeed-serial interfaces. The $17 (1000), self-clocking converter fits into a 1212mm LQFP-64 package and dissipates a maximum 192.5mW at its 250k-sample/sec conversion rate. In power-down mode, the dissipation falls to a maximum of 16.5µW. Reduced-resolution versions, the $12.95 (1000), 14-bit AD7657 and $10.60 (1000), 12-bit AD7658, are also available in the same package.
Commercial chip makers are by no means the only semiconductor manufacturers developing advanced high-voltage analog processes; foundry fabricators are keeping competitive, too.
Austriamicrosystems, for example, which operates both foundry services for fabless semiconductor companies and an IC-development organization for its own branded products, has developed the H35 high-voltage, 350nm, BiMOS process, which includes 20 and 50V MOS devices, bipolar transistors, capacitors, and high-resistivity polysilicon resistors.
The process can fabricate MOS devices with channel resistivities on the order of 0.04Ωmm2. Available libraries cover digital, analog, and high-voltage elements, as well as peripheral cells with high-output drive capability.
H35 is an automotive-qualified modular extension of a 350nm standard-CMOS process that Austriamicrosystems has licensed from TSMC. Despite its apparent flexibility, the extension adds only two mask layers to the basic process. According to Austriamicrosystems’ Full Service Foundry Senior Vice President Peter Gasteiner, the company “plans to fully characterize HV devices for 120V” in the future. Meanwhile, the company offers back-end assembly and test services to complement the primary fabrication service. The company also offers quarterly multiproject wafer shuttles, which can help reduce custom-silicondevelopment costs and time to market. A design kit compatible
with Agilent-ADS, Cadence, and Mentor Graphics environments includes simulation models, active and passive-device libraries, logic gates, peripheral cells, and simulation models for several IC packages.
Actuating the actuators
The 120V process goal that Gasteiner suggests may sound stratospheric, but several applications require such potentials and greater, particularly for optical, lighting, and transducer drivers. Goal Semiconductor, for example, offers these applications its HVDAC200 quad, high-voltage, 9-bit DAC. Each channel sums the output of its 9-bit main DAC with a 5-bit offset DAC—a calibration aid in many applications. Each sum drives one of the DAC’s four output stages, which are current sources that you can configure as a group for either 500µA or 5mA outputs. You can either select on-chip 600kΩresistors or connect external loads to convert current outputs to voltages. Be sure, however, not to exceed the output stage’s compliance voltage lest you clip the output.
In addition to the 5V nominal analog and digital power supplies, a 20 to 200V supply provides the current sources’ compliance voltage.
Additional on-chip facilities include a temperature sensor, a voltage reference, and overcurrent output protection. The $2 (production quantities) DAC’s maximum conversion rate is 17k samples/sec.
Its integral and differential nonlinearities are limited to ±0.5LSB.
Motor-drive amplifiers, at one time rack-mounted devices, have long been available as modules and hybrids for applications requiring moderate currents. Apex Microtechnology, a well-established company in the hybrid segment of the market, has developed a line of monolithic amplifiers. The company’s PA60 dual-amplifier IC can operate on split or unipolar supplies totaling 5 to 40V and delivers a peak 1A from a PSOP-20 package selling for $6.05 (100) or 1.5A from a SIP-12 package selling for $8.40 (100). Motor-drive applications include computer peripherals, automotives, and avionics.
The PA60 can form a full-bridge, bidirectional, variable-speed motor drive with one IC package and six external resistors (Figure 4). The amplifier provides a minimum 900kHz gain-bandwidth product and typical 13.6kHz full-power bandwidth. The outputs can swing to within 1.8V of the rail over temperature at 1A load current, and they slew at a minimum of 1V/µsec.
With 0.02% typical harmonic distortion, you could also use the PA60 as full- or half-bridge audio power amplifiers in medium-fidelity applications, such as external computer speakers.
Low-power-audio-amplifier applications, such as cell-phone- and laptop-speaker drivers, need to provide relatively large currents at low voltages for common low impedance dynamic transducers.
The current drain through the audio subsystem is one of the factors that tend to limit per-charge operating time in such devices. Panasonic Mobile Communications has reduced the space and power that the primary speaker in a mobilephone handset requires by replacing the dynamic driver with a smaller, high-impedance ceramic speaker, such as those from Taiyo Yuden.
Another emerging approach to reducing speaker footprint and power replaces the traditional speaker with a piezoelectric actuator, such as those from NXT.
These developments pose a common challenge to handset designers: The ceramic speakers and piezoelectric actuators both require higher drive voltages than those available from standard audio-poweramplifier ICs operating on lithiumion batteries. Unlike the dynamic speakers that they replace, ceramic speakers require as much as 12V pp; piezo speakers require 24V p-p.
National Semiconductor’s LM4960 piezo driver and the LM4961 ceramic-speaker driver each combine an on-chip boost converter with an audio power amplifier.
These newest members of National’s Boomer line feature a click-and-pop suppression circuit, which provides graceful transitions between operating states and a low-power shutdown mode. The LM4960’s boost converter operates at a fixed 1.6 MHz and drives a dual audio power-amplifier to deliver 24Vp-p in a full-bridge mono configuration with less than 1% THD. More typically, THD+noise is 0.04%. The amplifier’s minimum 50-dB powersupply rejection ratio reduces the effects of inband ripple on the low voltage supply input to inaudible levels. The $2.50 (1000) bridge amplifier provides overcurrent and over temperature shutdown as well as a shutdown mode you can invoke from your application.
The LM4961 includes a lowpower mode for ear buds, in which the amplifier operates on the power input from the phone’s lithium-ion battery. A high-power mode for ringtones and hands-free speakers uses the on-chip boost converter. In this mode, the driver can typically develop 15V p-p with less than 1% THD. The $2.10 (1000) amplifier’s maximum 14mA quiescent current drops to a maximum of 4mA in “receiver mode”—an active-standby mode that can track the phone’s transmit/receive switch. Shutdown current is no more than 2µA.
Design notes
Often as operating voltages increase, so does the available energy that an application must manage, both under normal operating conditions and under fault conditions.
Though circuit protection is rarely a concern beyond the power-supply design in applications that operate on a handful of volts or less, you may need to protect I/O nodes, particularly in systems operating on significantly higher voltages.
In I/O-subsystem designs that accommodate large input signals, be sure to compare the I/O device’s input topology and ratings, including input-protection circuits, with the expected range of signals under both normal and abnormal operating conditions. For example, if a field-wiring fault in a current-loop monitoring application can drive a nominal 10V input to a 48V rail, then you should determine the pin’s behavior at that elevated potential.
Most IC signal pins feature clamp structures that alleviate voltageoverstress conditions and suppress transients from ESD or similar events. There is a limit, however, to the amount of current the clamps can tolerate without sustaining damage. You may need to add a resistor in series with the input pin to limit the current below the damage threshold.
You can determine the lower limit on such a protection resistor’s value from the maximum sustainable fault voltage and the maximum tolerable pin current. Don’t forget that, in applications that span large areas, signals may be present when the power to the input device is off.
The positive clamp, in such a case, may be at ground potential rather than at the nominal supply.
Either noise concerns or the application’s tolerance for offset voltage and offset drift limit the resistor’s maximum value. Input bias currents, which these resistors convert into offset voltages, double every 10°C in MOS amplifiers, so include the maximum room temperature bias current and the maximum operating temperature in your calculations. As a side benefit in cases with input signals that require bandwidth limiting, the same resistor that protects the input from fault conditions can do double duty serving as the resistance in an RC lowpass filter.
Just as input structures may require external components to complement on-chip-protection features, so may outputs. Wiring faults or load failures can cause overcurrent conditions. Some devices provide explicit current limiting on their outputs or have output structures that are suitably robust as to tolerate their own shortcircuit current without sustaining damage. Others may require external protection, which may range from external current limiters to standard or resettable fuses. Load reactances can also complicate protection schemes by introducing fault modes that don’t exist with purely resistive loads. For example, a load that includes a large shunt capacitance looks like a short to ground during a power-up sequence. If input signals are present when you energize the output stage, large currents can f low while the load capacitance charges.
Similarly, large series load inductances from long wiring runs, for example, can develop inductive kickback voltages if a sudden change in load current occurs. Check your I/O-drive circuit’s overvoltage and overcurrent capability and any on-chip protection. Also check the phase margin when driving a load with a substantial reactive
component in a closed-loop topology.
Author information
You can reach Technical Editor Joshua Israelsohn at 1-781-734-8441, fax 1-781-290-3441, e-mail jisraelsohn@edn.com.
Acknowledgments
Thanks to Denis Doyle, Dick Meaney, and Craig Core of Analog Devices and Huibert Verhoeven of National Semiconductor for their contributions to this article.
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