Infineon Technologies AG and Nanya Technology Corp. has reported the successful qualification of 90nm DRAM technology, jointly developed at Infineon’s research center in Dresden, Germany.
Both companies have qualified the 90nm memory products at major customers and have achieved the validation of Intel. Volume production with 90nm process structures on 300mm has begun at Infineon’s 300mm production line in Dresden.
As of the end of May, approximately 5 percent of Infineon’s total global DRAM production has been converted from 110nm to 90nm.
Also, Inotera Memories, the Taiwan-based manufacturing joint venture of Infineon and Nanya, has begun transitioning to 90nm, the companies said.
Early adoption of 90nm is meant to improve production costs and product performances and is one of the most important factors to increase profitability in DRAM manufacturing, the companies believe.
Process structures of 90nm further reduce chip size compared to the previous 110nm technology thereby increasing potential chip output per wafer by more than 30 percent. The expected productivity increase by shrinking the chip size combined with the use of 300mm wafers is the basis for a significant reduction of production cost per chip.
Next, Infineon and Nanya will develop technology for the next node with 70nm structures under their strategic development alliance.
“With the qualification of advanced DRAM products on 90nm process technology we have achieved a major milestone towards product and technology leadership and increased DRAM manufacturing productivity,” said Andreas von Zitzewitz, member of Munich-based Infineon’s management board and head of its memory products business group, in a statement.
The introduction of 90nm process structures was helped along by the company’s experience with advanced 193nm lithography, introduced at the 110nm node, Infineon said.
Further, due to the introduction of so called “checkerboard cell array,” a superior storage capacitance could be achieved by just implementing standard surface enhancement methods instead of using complex high-k dielectrics.
Except for its cost advantage, transition to smaller process geometries is crucial for high-speed and low-power DDR2 and DDR3 SDRAM in an increasingly mobile world, the two said.
The companies plan to extend their DRAM offering with a 512Mb DDR2 SDRAM expected in the second half of the year, with a variety of other products including 256Mb DDR2 and 1G DDR2 to follow.
