Isolated FET Pulse Driver Increases Power Rate and Duty Cycle

In power converters, pulse-drive circuits transmit the pulses a controller generates to the power transistor. Driver circuits must both transmit the controller's switching on/off signals with galvanic isolation and provide energy to turn the switch on and off and to maintain the required on or off state. The required energy increases with the power transistor's input capacitance, which also increases with the power that the transistor module manages. Thus, when the circuit requires high power, designers typically parallel the power transistors, increasing the input capacitance. When you need to operate IGBT (insulated-gate-bipolar-transistor) modules in parallel, it is best to share the gate drive because using different driver circuits introduces additional variation in turn-on and -off times and creates a possible imbalance between each power module.

The basis of the circuit in Figure 1 is an earlier Design Idea (Reference 1). The operation of the circuits is basically the same as the one in the previous Design Idea, but this one can drive MOSFETs or IGBTs with input capacitances higher than 5nF. This circuit provides full galvanic isolation and requires no floating power supplies; it can transmit duty cycles that approach 100 percent.


Figure 1


This circuit adds transistors Q₆ and Q₇ to the circuit in the previous Design Idea. Transistors Q₁, Q₂, Q₃, and Q₄ are now higher power because they can manage a larger current depending on the transistor they need to drive. Transistors Q₁ and Q₂ are BUZ71 units, Q₃ and Q₄ are BUZ171 devices, and Q₆ and Q₇ are ZNV2106s. The differentiator circuits, C₁/R₁ and C₂/R₂, generate 1-μsec-long pulses, and you do not apply them directly to the gates of the Q₁ and Q₂ transistors, as in Reference 1, but to transistors Q₆ and Q₇. Although the input capacitances of Q₁ and Q₂ are nearly 700pF, the input capacitances of Q₆ and Q₇ are approximately 75pF, ensuring that the narrow pulses will transmit properly.

During the rising edge of the drive-control signal, Q₇ turns on, and its current starts charging the input capacitance of Q₂ through the on-resistance of Q₇. Because Q₇'s on-resistance is only a few ohms and no additional drain resistance exists, the charging process of Q₂'s input capacitance becomes fast, although its input capacitance is high.

As the gate voltage of Q₂ increases, the gate-to-source voltage of Q₇ decreases, and the transistor turns off. As a result, the narrow pulses that the differentiator circuit generates transmit to transistors Q₇ and Q₂ through coupling transformer T₁ to transistor Q₃, which charges Q₅'s gate-to-source input capacitance. The same process occurs with Q₆, Q₁, and Q₄ during the falling edge of the drive-control signal to discharge Q₅'s gate-to-source input capacitance.

With potentiometer P₁, you can control the discharge time of Q₁ and Q₂ and thus adjust the offset of the drive signal you apply to the power transistor. Because Q₆/Q₁ and Q₇/Q₂ transmit narrow pulses and have fast rising and falling edges, you can obtain a great duty-cycle variation even for high switching frequencies. You can control the duty cycle from 2 to 98 percent with a 20-kHz switching frequency. The circuit's compact design lets you mount it close to the power module, which minimizes parasitic elements.

Figure 2 shows the driver prototype for a 10-kW/20-kHz three-phase power inverter for grid injection. The circuit uses SKM75GB128 power transistors from Semikron (www.semikron.com). The transistors have a measured input capacitance higher than 15nF. In this situation, the total current consumption of the FET pulse driver is lower than 30mA.


Figure 2
References
1. Espí, José M, Rafael García-Gil, and Jaime Castelló, "Isolated FET pulse driver reduces size and power consumption," EDN, March 30, 2006, pg 98.