If one of your designs has not already called for a field-programmable gate array (FPGA), in all likelihood, you will have an FPGA-based design underway before long. Some engineers think many new electronic products will rely solely on memory and FPGA ICs, with analog circuits thrown in as “real world” interfaces. That approach means engineers unfamiliar with FPGAs should prepare themselves for a change in how they design digital circuits.
According to Malachy Devlin, chief technology officer at Nallatech, FPGAs have a big advantage over other digital circuits because they offer so much flexibility. On the other hand, he added, FPGAs have a big disadvantage because they offer so much flexibility. “You have an FPGA that can do almost anything, so you have many, many design choices,” said Devlin. “In a microprocessor-based design, engineers make fairly easy tradeoffs — the processor, the chipset, the memory interface and so on.” An FPGA design gets more complicated. Engineers must decide how to implement algorithms and memory and how to configure I/O ports, for example.
“Here is an example of an FPGA’s flexibility,” explained Devlin. “Engineers have an algorithm that needs to process data simultaneously with six coefficients. They can configure an FPGA with six physical banks of memory and perform six read operations at the same time. If they have a different algorithm that operates on longer words, they can convert the memory into three doublewide banks. That sort of flexibility illustrates how developers can adapt an FPGA’s memory to different algorithms.” But do not think of an FPGA as just supplying gates and simple functions. These days, FPGAs come with built-in memory structures, processors and specialized I/O controllers, too.
Thankfully, the tools used to design FPGA circuits insulate engineers from most implementation details. High-level FPGA design tools often use the computer languages VHDL (Figure 1) and Verilog to take the place of schematic symbols for individual functions. (See “FPGA Alphabet Soup” in the online version of this article.) But, digital designers need not master something new before they produce their first FPGA circuit.
“We hear from digital and board-level designers who lack experience with Verilog or VHDL,” noted Nick Martin, founder and chief executive officer of Altium. “When it comes time to design FPGA circuits, these engineers want to apply the techniques they already know.” To answer this need, Altium supplies libraries of building blocks that engineers can “assemble” on an FPGA. Other FPGA tools also provide the capability to design with schematics.
“Engineers can use Verilog or VHDL,” explained Martin, “but they do not have to. Instead, we provide high-level devices such as microprocessors and peripherals they can drop into a schematic. Or, they can write code if they choose.” Because the Altium software operates on top of tools from FPGA vendors, engineers need not learn how to operate tools from several vendors to use their FPGAs.
To help people make the transition from schematics to VHDL or Verilog designs, QuickLogic offers a design tool that lets engineers work with state diagrams. According to Brian Faith, QuickLogic’s senior director of logic products, “The tool generates code that engineers can use with other design software we offer. The tool also lets engineers see how the resulting code relates to their state-machine requirements. In a similar fashion, they can create a ‘test-bench’ by drawing digital waveforms that the simulator will apply to the design’s inputs.”
The QuickLogic QuickWorks software includes design-flow tutorials within its help files. “A mixed-mode design flow that joins schematics and code can ease engineers into using VHDL or Verilog,” said Faith. “The tutorials explain, for example, the steps needed to code a multiplexer in Verilog or to code a simple state machine in VHDL. So, engineers do not have to start from scratch. They can take what we provide and modify the code to get a fast start.”
Engineers just starting to learn VHDL or Verilog also can examine how their code relates to logic devices and blocks. “The HDL Analyst in our Synplify Pro software reads VHDL or Verilog code and converts it to a schematic,” explained Jeff Garrison, director of FPGA synthesis marketing at Synplicity. “If engineers code the function A + B = C, they will see a schematic of an adder and a multiplier. When they click on a function, they go back to the code that produced it.” Garrison noted even expert designers use the graphical output to ensure they get what they expected.
“We find fewer and fewer hardware designers who are unfamiliar with VHDL or Verilog,” said Chris Balough, director of software and Nios marketing at Altera. “Most logic designers we talk with have at least some experience with these languages, often gained during their engineering education. Some people still design with schematics, but even then, schematics often include symbols that represent VHDL or Verilog code.” So, Balough believes even engineers doing their first FPGA design have had some exposure to these design languages.
“At some point engineers must become familiar with Verilog or VHDL,” said Saloni Howard-Sarin, director of tools marketing at Actel. “If they haven’t worked with VHDL, for example, they can attend our two-day session on VHDL coding followed by three days of hands-on experience with the Libero design tools.”
To help engineers get started, FPGA suppliers and tool vendors offer a variety of development kits that come with many types of I/O devices and provide direct access to FPGA I/O pins (Figure 2). Prior to buying a kit, though, designers should investigate which FPGA family they expect to use and then purchase a kit that gives them an opportunity to try a device in that family. Usually, it makes sense to learn about one vendor’s FPGAs and then stick with them for the final design.
Starter kits cost from under $100 to several hundred dollars, so they provide an inexpensive way to learn what FPGA tools and devices offer. Walking through a simple tutorial that yields a functioning FPGA design usually takes a few hours. Tools shipped with kits may limit both the size of a design and the complexity of the FPGAs they work with. Often, vendors provide a kit version of their FPGA tools as free software engineers can download.
In addition to running through sample designs, engineers also can use reference designs with development kits. “We see a trend toward greater use of reference designs because engineers can quickly see how they work,” added Howard-Sarin of Actel. FPGA vendors also provide reference designs on their Web sites.
The NanoBoard development system from Altium (Figure 3) gives engineers “device independence.” Fifteen daughter cards let engineers choose a variety of FPGAs from Xilinx, Altera and Actel. Change the daughter board, and you target a different FPGA family. The NanoBoard comes with an LCD, LEDs, switches, memory and a variety of standard peripherals, which make it easy to test designs. When the time comes to move to a prototype or product, a configuration system in the Altium tools generates FPGA-specific files that get mapped into a vendor’s device. “You can have different configurations for different targets,” explained Martin.
Engineers who have developed ASICs find FPGA design somewhat different, said Chris Balough of Altera. “An FPGA implements logic in a different way. It looks like a matrix of look-up tables and flip-flops. That’s why tool suppliers abstract users from device details.”
Jeff Garrison at Synplicity offered a specific design difference. “ASIC designers will instantiate, or establish, a specific memory structure, but we recommend FPGA developers describe memory generically. Then our tools can infer the memory requirements. That approach lets the tool select an appropriate memory implementation based on performance and available resources. And developers get a greater degree of design portability. If you instantiate a Vendor-A RAM, that usually ties you to Vendor-A’s FPGA chips.”
Engineers who develop ASICs also discover FPGA design is more like software development than hardware design. “Because FPGA designers have the tools on their desktop PC, they tend to work like software programmers,” said Actel’s Howard-Sarin. “They take a try-it-and-see-if-it-works approach. If it does not work, they adjust their design. ASIC engineers who move into FPGA design say, ‘What do I do for formal verification?’ Well, you just try the design.” (Large FPGA designs generally need formal verification, though.)
Designers entering FPGA designs with a C/C++ or Java background need to understand timing. A design tip from Xilinx illustrates how FPGA designers use synchronous circuits in a design. In the first circuit (Figure 4a), the enable signal can occur at any time, which may cause a glitch in the flip-flop’s clock signal. The second circuit (Figure 4b) clocks the flip-flop directly and uses the enable signal to select the flip-flop’s D input. Clocking can occur only on the clock edge. Many design tools handle this type of synchronous action automatically, but designers should understand an FPGA’s timing requirements.
